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Commit 7d48fa5e authored by mbrandy's avatar mbrandy Committed by Commit bot
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PPC: [wasm] Int64Lowering of I64ShrU and I64ShrS. 

Port 240b7db9

R=ahaas@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1780283002

Cr-Commit-Position: refs/heads/master@{#34694}
parent d9c45337
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Showing with 145 additions and 20 deletions
src/compiler/ppc/code-generator-ppc.cc
View file @ 7d48fa5e
...@@ -966,17 +966,39 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) { ...@@ -966,17 +966,39 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
break; break;
#endif #endif
#if !V8_TARGET_ARCH_PPC64 #if !V8_TARGET_ARCH_PPC64
case kPPC_PairShiftLeft: case kPPC_ShiftLeftPair:
if (instr->InputAt(2)->IsImmediate()) { if (instr->InputAt(2)->IsImmediate()) {
__ PairShiftLeft(i.OutputRegister(0), i.OutputRegister(1), __ ShiftLeftPair(i.OutputRegister(0), i.OutputRegister(1),
i.InputRegister(0), i.InputRegister(1), i.InputRegister(0), i.InputRegister(1),
i.InputInt32(2)); i.InputInt32(2));
} else { } else {
__ PairShiftLeft(i.OutputRegister(0), i.OutputRegister(1), __ ShiftLeftPair(i.OutputRegister(0), i.OutputRegister(1),
i.InputRegister(0), i.InputRegister(1), kScratchReg, i.InputRegister(0), i.InputRegister(1), kScratchReg,
i.InputRegister(2)); i.InputRegister(2));
} }
break; break;
case kPPC_ShiftRightPair:
if (instr->InputAt(2)->IsImmediate()) {
__ ShiftRightPair(i.OutputRegister(0), i.OutputRegister(1),
i.InputRegister(0), i.InputRegister(1),
i.InputInt32(2));
} else {
__ ShiftRightPair(i.OutputRegister(0), i.OutputRegister(1),
i.InputRegister(0), i.InputRegister(1), kScratchReg,
i.InputRegister(2));
}
break;
case kPPC_ShiftRightAlgPair:
if (instr->InputAt(2)->IsImmediate()) {
__ ShiftRightAlgPair(i.OutputRegister(0), i.OutputRegister(1),
i.InputRegister(0), i.InputRegister(1),
i.InputInt32(2));
} else {
__ ShiftRightAlgPair(i.OutputRegister(0), i.OutputRegister(1),
i.InputRegister(0), i.InputRegister(1),
kScratchReg, i.InputRegister(2));
}
break;
#endif #endif
case kPPC_RotRight32: case kPPC_RotRight32:
if (HasRegisterInput(instr, 1)) { if (HasRegisterInput(instr, 1)) {
......
src/compiler/ppc/instruction-codes-ppc.h
View file @ 7d48fa5e
...@@ -19,11 +19,13 @@ namespace compiler { ...@@ -19,11 +19,13 @@ namespace compiler {
V(PPC_Xor) \ V(PPC_Xor) \
V(PPC_ShiftLeft32) \ V(PPC_ShiftLeft32) \
V(PPC_ShiftLeft64) \ V(PPC_ShiftLeft64) \
V(PPC_ShiftLeftPair) \
V(PPC_ShiftRight32) \ V(PPC_ShiftRight32) \
V(PPC_ShiftRight64) \ V(PPC_ShiftRight64) \
V(PPC_ShiftRightPair) \
V(PPC_ShiftRightAlg32) \ V(PPC_ShiftRightAlg32) \
V(PPC_ShiftRightAlg64) \ V(PPC_ShiftRightAlg64) \
V(PPC_PairShiftLeft) \ V(PPC_ShiftRightAlgPair) \
V(PPC_RotRight32) \ V(PPC_RotRight32) \
V(PPC_RotRight64) \ V(PPC_RotRight64) \
V(PPC_Not) \ V(PPC_Not) \
......
src/compiler/ppc/instruction-scheduler-ppc.cc
View file @ 7d48fa5e
...@@ -21,11 +21,13 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -21,11 +21,13 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_Xor: case kPPC_Xor:
case kPPC_ShiftLeft32: case kPPC_ShiftLeft32:
case kPPC_ShiftLeft64: case kPPC_ShiftLeft64:
case kPPC_ShiftLeftPair:
case kPPC_ShiftRight32: case kPPC_ShiftRight32:
case kPPC_ShiftRight64: case kPPC_ShiftRight64:
case kPPC_ShiftRightPair:
case kPPC_ShiftRightAlg32: case kPPC_ShiftRightAlg32:
case kPPC_ShiftRightAlg64: case kPPC_ShiftRightAlg64:
case kPPC_PairShiftLeft: case kPPC_ShiftRightAlgPair:
case kPPC_RotRight32: case kPPC_RotRight32:
case kPPC_RotRight64: case kPPC_RotRight64:
case kPPC_Not: case kPPC_Not:
......
src/compiler/ppc/instruction-selector-ppc.cc
View file @ 7d48fa5e
...@@ -723,12 +723,6 @@ void InstructionSelector::VisitWord32Shr(Node* node) { ...@@ -723,12 +723,6 @@ void InstructionSelector::VisitWord32Shr(Node* node) {
VisitRRO(this, kPPC_ShiftRight32, node, kShift32Imm); VisitRRO(this, kPPC_ShiftRight32, node, kShift32Imm);
} }
#if !V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord32PairShr(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitWord32PairSar(Node* node) { UNIMPLEMENTED(); }
#endif
#if V8_TARGET_ARCH_PPC64 #if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Shr(Node* node) { void InstructionSelector::VisitWord64Shr(Node* node) {
PPCOperandGenerator g(this); PPCOperandGenerator g(this);
...@@ -791,8 +785,9 @@ void InstructionSelector::VisitWord32Sar(Node* node) { ...@@ -791,8 +785,9 @@ void InstructionSelector::VisitWord32Sar(Node* node) {
} }
#if !V8_TARGET_ARCH_PPC64 #if !V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord32PairShl(Node* node) { void VisitPairShift(InstructionSelector* selector, ArchOpcode opcode,
PPCOperandGenerator g(this); Node* node) {
PPCOperandGenerator g(selector);
Int32Matcher m(node->InputAt(2)); Int32Matcher m(node->InputAt(2));
InstructionOperand shift_operand; InstructionOperand shift_operand;
if (m.HasValue()) { if (m.HasValue()) {
...@@ -809,7 +804,19 @@ void InstructionSelector::VisitWord32PairShl(Node* node) { ...@@ -809,7 +804,19 @@ void InstructionSelector::VisitWord32PairShl(Node* node) {
g.DefineSameAsFirst(node), g.DefineSameAsFirst(node),
g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
Emit(kPPC_PairShiftLeft, 2, outputs, 3, inputs); selector->Emit(opcode, 2, outputs, 3, inputs);
}
void InstructionSelector::VisitWord32PairShl(Node* node) {
VisitPairShift(this, kPPC_ShiftLeftPair, node);
}
void InstructionSelector::VisitWord32PairShr(Node* node) {
VisitPairShift(this, kPPC_ShiftRightPair, node);
}
void InstructionSelector::VisitWord32PairSar(Node* node) {
VisitPairShift(this, kPPC_ShiftRightAlgPair, node);
} }
#endif #endif
......
src/ppc/macro-assembler-ppc.cc
View file @ 7d48fa5e
...@@ -831,7 +831,7 @@ void MacroAssembler::ConvertDoubleToUnsignedInt64( ...@@ -831,7 +831,7 @@ void MacroAssembler::ConvertDoubleToUnsignedInt64(
#endif #endif
#if !V8_TARGET_ARCH_PPC64 #if !V8_TARGET_ARCH_PPC64
void MacroAssembler::PairShiftLeft(Register dst_low, Register dst_high, void MacroAssembler::ShiftLeftPair(Register dst_low, Register dst_high,
Register src_low, Register src_high, Register src_low, Register src_high,
Register scratch, Register shift) { Register scratch, Register shift) {
DCHECK(!AreAliased(dst_low, src_high, shift)); DCHECK(!AreAliased(dst_low, src_high, shift));
...@@ -855,13 +855,11 @@ void MacroAssembler::PairShiftLeft(Register dst_low, Register dst_high, ...@@ -855,13 +855,11 @@ void MacroAssembler::PairShiftLeft(Register dst_low, Register dst_high,
bind(&done); bind(&done);
} }
void MacroAssembler::PairShiftLeft(Register dst_low, Register dst_high, void MacroAssembler::ShiftLeftPair(Register dst_low, Register dst_high,
Register src_low, Register src_high, Register src_low, Register src_high,
uint32_t shift) { uint32_t shift) {
DCHECK(!AreAliased(dst_low, src_high)); DCHECK(!AreAliased(dst_low, src_high));
DCHECK(!AreAliased(dst_high, src_low)); DCHECK(!AreAliased(dst_high, src_low));
Label less_than_32;
Label done;
if (shift >= 32) { if (shift >= 32) {
shift &= 0x1f; shift &= 0x1f;
slwi(dst_high, src_low, Operand(shift)); slwi(dst_high, src_low, Operand(shift));
...@@ -875,6 +873,92 @@ void MacroAssembler::PairShiftLeft(Register dst_low, Register dst_high, ...@@ -875,6 +873,92 @@ void MacroAssembler::PairShiftLeft(Register dst_low, Register dst_high,
slwi(dst_low, src_low, Operand(shift)); slwi(dst_low, src_low, Operand(shift));
} }
} }
void MacroAssembler::ShiftRightPair(Register dst_low, Register dst_high,
Register src_low, Register src_high,
Register scratch, Register shift) {
DCHECK(!AreAliased(dst_low, src_high, shift));
DCHECK(!AreAliased(dst_high, src_low, shift));
Label less_than_32;
Label done;
cmpi(shift, Operand(32));
blt(&less_than_32);
// If shift >= 32
andi(scratch, shift, Operand(0x1f));
srw(dst_low, src_high, scratch);
li(dst_high, Operand::Zero());
b(&done);
bind(&less_than_32);
// If shift < 32
subfic(scratch, shift, Operand(32));
srw(dst_low, src_low, shift);
slw(scratch, src_high, scratch);
orx(dst_low, dst_low, scratch);
srw(dst_high, src_high, shift);
bind(&done);
}
void MacroAssembler::ShiftRightPair(Register dst_low, Register dst_high,
Register src_low, Register src_high,
uint32_t shift) {
DCHECK(!AreAliased(dst_low, src_high));
DCHECK(!AreAliased(dst_high, src_low));
if (shift >= 32) {
shift &= 0x1f;
srwi(dst_low, src_high, Operand(shift));
li(dst_high, Operand::Zero());
} else if (shift == 0) {
Move(dst_low, src_low);
Move(dst_high, src_high);
} else {
srwi(dst_low, src_low, Operand(shift));
rlwimi(dst_low, src_high, 32 - shift, 0, shift - 1);
srwi(dst_high, src_high, Operand(shift));
}
}
void MacroAssembler::ShiftRightAlgPair(Register dst_low, Register dst_high,
Register src_low, Register src_high,
Register scratch, Register shift) {
DCHECK(!AreAliased(dst_low, src_high, shift));
DCHECK(!AreAliased(dst_high, src_low, shift));
Label less_than_32;
Label done;
cmpi(shift, Operand(32));
blt(&less_than_32);
// If shift >= 32
andi(scratch, shift, Operand(0x1f));
sraw(dst_low, src_high, scratch);
srawi(dst_high, src_high, 31);
b(&done);
bind(&less_than_32);
// If shift < 32
subfic(scratch, shift, Operand(32));
srw(dst_low, src_low, shift);
slw(scratch, src_high, scratch);
orx(dst_low, dst_low, scratch);
sraw(dst_high, src_high, shift);
bind(&done);
}
void MacroAssembler::ShiftRightAlgPair(Register dst_low, Register dst_high,
Register src_low, Register src_high,
uint32_t shift) {
DCHECK(!AreAliased(dst_low, src_high));
DCHECK(!AreAliased(dst_high, src_low));
if (shift >= 32) {
shift &= 0x1f;
srawi(dst_low, src_high, shift);
srawi(dst_high, src_high, 31);
} else if (shift == 0) {
Move(dst_low, src_low);
Move(dst_high, src_high);
} else {
srwi(dst_low, src_low, Operand(shift));
rlwimi(dst_low, src_high, 32 - shift, 0, shift - 1);
srawi(dst_high, src_high, shift);
}
}
#endif #endif
void MacroAssembler::LoadConstantPoolPointerRegisterFromCodeTargetAddress( void MacroAssembler::LoadConstantPoolPointerRegisterFromCodeTargetAddress(
......
src/ppc/macro-assembler-ppc.h
View file @ 7d48fa5e
...@@ -415,10 +415,18 @@ class MacroAssembler : public Assembler { ...@@ -415,10 +415,18 @@ class MacroAssembler : public Assembler {
#endif #endif
#if !V8_TARGET_ARCH_PPC64 #if !V8_TARGET_ARCH_PPC64
void PairShiftLeft(Register dst_low, Register dst_high, Register src_low, void ShiftLeftPair(Register dst_low, Register dst_high, Register src_low,
Register src_high, Register scratch, Register shift); Register src_high, Register scratch, Register shift);
void PairShiftLeft(Register dst_low, Register dst_high, Register src_low, void ShiftLeftPair(Register dst_low, Register dst_high, Register src_low,
Register src_high, uint32_t shift); Register src_high, uint32_t shift);
void ShiftRightPair(Register dst_low, Register dst_high, Register src_low,
Register src_high, Register scratch, Register shift);
void ShiftRightPair(Register dst_low, Register dst_high, Register src_low,
Register src_high, uint32_t shift);
void ShiftRightAlgPair(Register dst_low, Register dst_high, Register src_low,
Register src_high, Register scratch, Register shift);
void ShiftRightAlgPair(Register dst_low, Register dst_high, Register src_low,
Register src_high, uint32_t shift);
#endif #endif
// Generates function and stub prologue code. // Generates function and stub prologue code.
......
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