Commit 7d1d83e5 authored by sampsong's avatar sampsong Committed by Commit bot

PPC: Declare XX3 format assembler function with opcode list macro

BUG=

R=bjaideep@ca.ibm.com, jyan@ca.ibm.com, joransiu@ca.ibm.com

Review-Url: https://codereview.chromium.org/2712193002
Cr-Commit-Position: refs/heads/master@{#43456}
parent 60991f99
......@@ -651,15 +651,6 @@ void Assembler::xo_form(Instr instr, Register rt, Register ra, Register rb,
emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 | o | r);
}
void Assembler::xx3_form(Instr instr, DoubleRegister t, DoubleRegister a,
DoubleRegister b) {
int AX = ((a.code() & 0x20) >> 5) & 0x1;
int BX = ((b.code() & 0x20) >> 5) & 0x1;
int TX = ((t.code() & 0x20) >> 5) & 0x1;
emit(instr | (t.code() & 0x1F) * B21 | (a.code() & 0x1F) * B16 | (b.code()
& 0x1F) * B11 | AX * B2 | BX * B1 | TX);
}
void Assembler::md_form(Instr instr, Register ra, Register rs, int shift,
int maskbit, RCBit r) {
int sh0_4 = shift & 0x1f;
......@@ -2355,25 +2346,6 @@ void Assembler::fmsub(const DoubleRegister frt, const DoubleRegister fra,
frc.code() * B6 | rc);
}
// Support for VSX instructions
void Assembler::xsadddp(const DoubleRegister frt, const DoubleRegister fra,
const DoubleRegister frb) {
xx3_form(EXT6 | XSADDDP, frt, fra, frb);
}
void Assembler::xssubdp(const DoubleRegister frt, const DoubleRegister fra,
const DoubleRegister frb) {
xx3_form(EXT6 | XSSUBDP, frt, fra, frb);
}
void Assembler::xsdivdp(const DoubleRegister frt, const DoubleRegister fra,
const DoubleRegister frb) {
xx3_form(EXT6 | XSDIVDP, frt, fra, frb);
}
void Assembler::xsmuldp(const DoubleRegister frt, const DoubleRegister fra,
const DoubleRegister frb) {
xx3_form(EXT6 | XSMULDP, frt, fra, frb);
}
// Pseudo instructions.
void Assembler::nop(int type) {
Register reg = r0;
......
......@@ -553,6 +553,25 @@ class Assembler : public AssemblerBase {
return ((cr.code() * CRWIDTH) + crbit);
}
#define DECLARE_PPC_XX3_INSTRUCTIONS(name, instr_name, instr_value) \
inline void name(const DoubleRegister rt, const DoubleRegister ra, \
const DoubleRegister rb) { \
xx3_form(instr_name, rt, ra, rb); \
}
inline void xx3_form(Instr instr, DoubleRegister t, DoubleRegister a,
DoubleRegister b) {
int AX = ((a.code() & 0x20) >> 5) & 0x1;
int BX = ((b.code() & 0x20) >> 5) & 0x1;
int TX = ((t.code() & 0x20) >> 5) & 0x1;
emit(instr | (t.code() & 0x1F) * B21 | (a.code() & 0x1F) * B16 |
(b.code() & 0x1F) * B11 | AX * B2 | BX * B1 | TX);
}
PPC_XX3_OPCODE_LIST(DECLARE_PPC_XX3_INSTRUCTIONS)
#undef DECLARE_PPC_XX3_INSTRUCTIONS
// ---------------------------------------------------------------------------
// Code generation
......@@ -1102,17 +1121,6 @@ class Assembler : public AssemblerBase {
const DoubleRegister frc, const DoubleRegister frb,
RCBit rc = LeaveRC);
// Support for VSX instructions
void xsadddp(const DoubleRegister frt, const DoubleRegister fra,
const DoubleRegister frb);
void xssubdp(const DoubleRegister frt, const DoubleRegister fra,
const DoubleRegister frb);
void xsdivdp(const DoubleRegister frt, const DoubleRegister fra,
const DoubleRegister frb);
void xsmuldp(const DoubleRegister frt, const DoubleRegister fra,
const DoubleRegister frc);
// Pseudo instructions
// Different nop operations are used by the code generator to detect certain
......@@ -1415,8 +1423,6 @@ class Assembler : public AssemblerBase {
void x_form(Instr instr, Register ra, Register rs, Register rb, RCBit r);
void xo_form(Instr instr, Register rt, Register ra, Register rb, OEBit o,
RCBit r);
void xx3_form(Instr instr, DoubleRegister t, DoubleRegister a,
DoubleRegister b);
void md_form(Instr instr, Register ra, Register rs, int shift, int maskbit,
RCBit r);
void mds_form(Instr instr, Register ra, Register rs, Register rb, int maskbit,
......
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