Fix assembler for packed move instructions

The AVX version should only take one argument, so these instructions have
to be split from the main list of SSE4 instructions, whose AVX version
have two arguments.

Bug: v8:9886
Change-Id: Ie37e060711babd7760547e2aa01c9c0fb0c728b5
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1986215
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65588}

src/codegen/x64/assembler-x64.h

@@ -958,6 +958,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   }
 
   SSE4_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION)
+  SSE4_PMOV_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION)
 #undef DECLARE_SSE4_INSTRUCTION
 
 #define DECLARE_SSE4_EXTRACT_INSTRUCTION(instruction, prefix, escape1,     \
@@ -1004,6 +1005,17 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   SSE4_INSTRUCTION_LIST(DECLARE_SSE34_AVX_INSTRUCTION)
 #undef DECLARE_SSE34_AVX_INSTRUCTION
 
+#define DECLARE_SSE4_PMOV_AVX_INSTRUCTION(instruction, prefix, escape1,      \
+                                          escape2, opcode)                   \
+  void v##instruction(XMMRegister dst, XMMRegister src) {                    \
+    vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
+  }                                                                          \
+  void v##instruction(XMMRegister dst, Operand src) {                        \
+    vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
+  }
+  SSE4_PMOV_INSTRUCTION_LIST(DECLARE_SSE4_PMOV_AVX_INSTRUCTION)
+#undef DECLARE_SSE4_PMOV_AVX_INSTRUCTION
+
   void movd(XMMRegister dst, Register src);
   void movd(XMMRegister dst, Operand src);
   void movd(Register dst, XMMRegister src);

src/codegen/x64/sse-instr.h

@@ -135,13 +135,7 @@
   V(blendvpd, 66, 0F, 38, 15)    \
   V(pcmpeqq, 66, 0F, 38, 29)     \
   V(ptest, 66, 0F, 38, 17)       \
-  V(pmovsxbw, 66, 0F, 38, 20)    \
-  V(pmovsxwd, 66, 0F, 38, 23)    \
-  V(pmovsxdq, 66, 0F, 38, 25)    \
   V(packusdw, 66, 0F, 38, 2B)    \
-  V(pmovzxbw, 66, 0F, 38, 30)    \
-  V(pmovzxwd, 66, 0F, 38, 33)    \
-  V(pmovzxdq, 66, 0F, 38, 35)    \
   V(pminsb, 66, 0F, 38, 38)      \
   V(pminsd, 66, 0F, 38, 39)      \
   V(pminuw, 66, 0F, 38, 3A)      \
@@ -152,6 +146,15 @@
   V(pmaxud, 66, 0F, 38, 3F)      \
   V(pmulld, 66, 0F, 38, 40)
 
+// SSE instructions whose AVX version has two operands.
+#define SSE4_PMOV_INSTRUCTION_LIST(V) \
+  V(pmovsxbw, 66, 0F, 38, 20)         \
+  V(pmovsxwd, 66, 0F, 38, 23)         \
+  V(pmovsxdq, 66, 0F, 38, 25)         \
+  V(pmovzxbw, 66, 0F, 38, 30)         \
+  V(pmovzxwd, 66, 0F, 38, 33)         \
+  V(pmovzxdq, 66, 0F, 38, 35)
+
 #define SSE4_EXTRACT_INSTRUCTION_LIST(V) \
   V(extractps, 66, 0F, 3A, 17)           \
   V(pextrb, 66, 0F, 3A, 14)              \

src/diagnostics/x64/disasm-x64.cc

@@ -917,6 +917,17 @@ int DisassemblerX64::AVXInstruction(byte* data) {
         SSSE3_INSTRUCTION_LIST(DECLARE_SSE_AVX_DIS_CASE)
         SSE4_INSTRUCTION_LIST(DECLARE_SSE_AVX_DIS_CASE)
 #undef DECLARE_SSE_AVX_DIS_CASE
+
+#define DECLARE_SSE_PMOV_AVX_DIS_CASE(instruction, notUsed1, notUsed2, \
+                                      notUsed3, opcode)                \
+  case 0x##opcode: {                                                   \
+    AppendToBuffer("v" #instruction " %s,", NameOfXMMRegister(regop)); \
+    current += PrintRightXMMOperand(current);                          \
+    break;                                                             \
+  }
+        SSE4_PMOV_INSTRUCTION_LIST(DECLARE_SSE_PMOV_AVX_DIS_CASE)
+#undef DECLARE_SSE_PMOV_AVX_DIS_CASE
+
       default:
         UnimplementedInstruction();
     }
@@ -1757,6 +1768,7 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
 
         SSSE3_INSTRUCTION_LIST(SSE34_DIS_CASE)
         SSE4_INSTRUCTION_LIST(SSE34_DIS_CASE)
+        SSE4_PMOV_INSTRUCTION_LIST(SSE34_DIS_CASE)
         SSE4_2_INSTRUCTION_LIST(SSE34_DIS_CASE)
 #undef SSE34_DIS_CASE
         default:

test/cctest/test-disasm-x64.cc

@@ -567,6 +567,7 @@ TEST(DisasmX64) {
       __ cvtdq2ps(xmm5, Operand(rdx, 4));
 
       SSE4_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
+      SSE4_PMOV_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
       SSE4_EXTRACT_INSTRUCTION_LIST(EMIT_SSE34_IMM_INSTR)
     }
   }
@@ -740,6 +741,13 @@ TEST(DisasmX64) {
 #undef EMIT_SSE2_AVXINSTR
 #undef EMIT_SSE34_AVXINSTR
 
+#define EMIT_SSE4_PMOV_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3, \
+                                notUsed4)                                  \
+  __ v##instruction(xmm10, xmm1);                                          \
+  __ v##instruction(xmm10, Operand(rdx, 4));
+      SSE4_PMOV_INSTRUCTION_LIST(EMIT_SSE4_PMOV_AVXINSTR)
+#undef EMIT_SSE4_PMOV_AVXINSTR
+
 #define EMIT_SSE2_SHIFT_IMM_AVX(instruction, notUsed1, notUsed2, notUsed3, \
                                 notUsed4)                                  \
   __ v##instruction(xmm0, xmm15, 21);