Commit 7cdcf0b1 authored by alph's avatar alph Committed by Commit bot

[x64] Use vcvtlsi2sd when AVX is enabled

BUG=v8:4406
LOG=N

Committed: https://crrev.com/adcbe619a959fe1d8f21d06fbf5984868c4f6b9a
Cr-Commit-Position: refs/heads/master@{#31276}

Review URL: https://codereview.chromium.org/1404903004

Cr-Commit-Position: refs/heads/master@{#31315}
parent e5db1d58
......@@ -922,9 +922,9 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
}
case kSSEInt32ToFloat64:
if (instr->InputAt(0)->IsRegister()) {
__ cvtlsi2sd(i.OutputDoubleRegister(), i.InputRegister(0));
__ Cvtlsi2sd(i.OutputDoubleRegister(), i.InputRegister(0));
} else {
__ cvtlsi2sd(i.OutputDoubleRegister(), i.InputOperand(0));
__ Cvtlsi2sd(i.OutputDoubleRegister(), i.InputOperand(0));
}
break;
case kSSEUint32ToFloat64:
......
......@@ -3065,6 +3065,7 @@ void Assembler::cvttsd2siq(Register dst, const Operand& src) {
void Assembler::cvtlsi2sd(XMMRegister dst, const Operand& src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
......@@ -3075,6 +3076,7 @@ void Assembler::cvtlsi2sd(XMMRegister dst, const Operand& src) {
void Assembler::cvtlsi2sd(XMMRegister dst, Register src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
......
......@@ -1313,6 +1313,13 @@ class Assembler : public AssemblerBase {
void vminsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
vsd(0x5d, dst, src1, src2);
}
void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, Register src2) {
XMMRegister isrc2 = {src2.code()};
vsd(0x2a, dst, src1, isrc2);
}
void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
vsd(0x2a, dst, src1, src2);
}
void vucomisd(XMMRegister dst, XMMRegister src);
void vucomisd(XMMRegister dst, const Operand& src);
void vsd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
......
......@@ -997,6 +997,11 @@ int DisassemblerX64::AVXInstruction(byte* data) {
current += PrintRightXMMOperand(current);
AppendToBuffer(",%s", NameOfXMMRegister(regop));
break;
case 0x2a:
AppendToBuffer("vcvtlsi2sd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightOperand(current);
break;
case 0x58:
AppendToBuffer("vaddsd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
......
......@@ -4774,7 +4774,7 @@ void LCodeGen::DoDeferredNumberTagIU(LInstruction* instr,
// the value in there. If that fails, call the runtime system.
__ SmiToInteger32(reg, reg);
__ xorl(reg, Immediate(0x80000000));
__ cvtlsi2sd(temp_xmm, reg);
__ Cvtlsi2sd(temp_xmm, reg);
} else {
DCHECK(signedness == UNSIGNED_INT32);
__ LoadUint32(temp_xmm, reg);
......
......@@ -788,14 +788,26 @@ void MacroAssembler::PopCallerSaved(SaveFPRegsMode fp_mode,
void MacroAssembler::Cvtlsi2sd(XMMRegister dst, Register src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vxorpd(dst, dst, dst);
vcvtlsi2sd(dst, dst, src);
} else {
xorps(dst, dst);
cvtlsi2sd(dst, src);
}
}
void MacroAssembler::Cvtlsi2sd(XMMRegister dst, const Operand& src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vxorpd(dst, dst, dst);
vcvtlsi2sd(dst, dst, src);
} else {
xorps(dst, dst);
cvtlsi2sd(dst, src);
}
}
......
......@@ -1359,6 +1359,13 @@ TEST(AssemblerX64AVX_sd) {
__ vmovsd(xmm5, Operand(rsp, kDoubleSize));
__ vmovsd(xmm6, xmm5);
__ vmovapd(xmm3, xmm6);
__ movl(rdx, Immediate(6));
__ vcvtlsi2sd(xmm6, xmm6, rdx);
__ movl(Operand(rsp, 0), Immediate(5));
__ vcvtlsi2sd(xmm7, xmm7, Operand(rsp, 0));
__ vsubsd(xmm7, xmm6, xmm7); // xmm7 is 1.0
__ vmulsd(xmm1, xmm1, xmm7);
__ addq(rsp, Immediate(kDoubleSize * 2));
__ vucomisd(xmm3, xmm1);
......
......@@ -530,6 +530,8 @@ TEST(DisasmX64) {
__ vmaxsd(xmm9, xmm1, Operand(rbx, rcx, times_1, 10000));
__ vucomisd(xmm9, xmm1);
__ vucomisd(xmm8, Operand(rbx, rdx, times_2, 10981));
__ vcvtlsi2sd(xmm5, xmm9, rcx);
__ vcvtlsi2sd(xmm9, xmm3, Operand(rbx, r9, times_4, 10000));
__ vandps(xmm0, xmm9, xmm2);
__ vandps(xmm9, xmm1, Operand(rbx, rcx, times_4, 10000));
......
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