Commit 7beeae4a authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ

PPC [simd]: optimize I16x8Mul in codegen

Change-Id: I7174f13634112f9cc185fb422fb15cb6ea0b2dd5
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3015517Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#75648}
parent 53574525
......@@ -2441,14 +2441,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
__ vmuleuh(kScratchSimd128Reg, src0, src1);
__ vmulouh(i.OutputSimd128Register(), src0, src1);
__ xxspltib(tempFPReg1, Operand(16));
__ vslw(kScratchSimd128Reg, kScratchSimd128Reg, tempFPReg1);
__ vslw(dst, dst, tempFPReg1);
__ vsrw(dst, dst, tempFPReg1);
__ vor(dst, kScratchSimd128Reg, dst);
__ vxor(kScratchSimd128Reg, kScratchSimd128Reg, kScratchSimd128Reg);
__ vmladduhm(dst, src0, src1, kScratchSimd128Reg);
break;
}
case kPPC_I8x16Add: {
......
......@@ -4917,6 +4917,20 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
}
break;
}
case VMLADDUHM: {
int vrt = instr->RTValue();
int vra = instr->RAValue();
int vrb = instr->RBValue();
int vrc = instr->RCValue();
FOR_EACH_LANE(i, uint16_t) {
uint16_t vra_val = get_simd_register_by_lane<uint16_t>(vra, i);
uint16_t vrb_val = get_simd_register_by_lane<uint16_t>(vrb, i);
uint16_t vrc_val = get_simd_register_by_lane<uint16_t>(vrc, i);
set_simd_register_by_lane<uint16_t>(vrt, i,
(vra_val * vrb_val) + vrc_val);
}
break;
}
#define VECTOR_UNARY_OP(type, op) \
int t = instr->RTValue(); \
int b = instr->RBValue(); \
......
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