Commit 7aa8cb46 authored by rmcilroy@chromium.org's avatar rmcilroy@chromium.org

[Arm]: Make Assembler::movw only emit a movw instruction.

Currently Assembler::movw is really the mov macro instruction, leading to raw
emit calls to generate the real movw instruction. Replace all calls of mow
with the mov macro instruction (which will emit a movw if appropriate) and
make movw always emit movw.

R=ulan@chromium.org

Review URL: https://codereview.chromium.org/329233002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22085 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
parent c1e67437
...@@ -1092,8 +1092,7 @@ void Assembler::move_32_bit_immediate(Register rd, ...@@ -1092,8 +1092,7 @@ void Assembler::move_32_bit_immediate(Register rd,
// Make sure the movw/movt doesn't get separated. // Make sure the movw/movt doesn't get separated.
BlockConstPoolFor(2); BlockConstPoolFor(2);
} }
emit(cond | 0x30*B20 | target.code()*B12 | movw(target, static_cast<uint32_t>(x.imm32_ & 0xffff), cond);
EncodeMovwImmediate(x.imm32_ & 0xffff));
movt(target, static_cast<uint32_t>(x.imm32_) >> 16, cond); movt(target, static_cast<uint32_t>(x.imm32_) >> 16, cond);
if (target.code() != rd.code()) { if (target.code() != rd.code()) {
mov(rd, target, LeaveCC, cond); mov(rd, target, LeaveCC, cond);
...@@ -1457,11 +1456,7 @@ void Assembler::mov_label_offset(Register dst, Label* label) { ...@@ -1457,11 +1456,7 @@ void Assembler::mov_label_offset(Register dst, Label* label) {
void Assembler::movw(Register reg, uint32_t immediate, Condition cond) { void Assembler::movw(Register reg, uint32_t immediate, Condition cond) {
ASSERT(immediate < 0x10000); emit(cond | 0x30*B20 | reg.code()*B12 | EncodeMovwImmediate(immediate));
// May use movw if supported, but on unsupported platforms will try to use
// equivalent rotated immed_8 value and other tricks before falling back to a
// constant pool load.
mov(reg, Operand(immediate), LeaveCC, cond);
} }
......
...@@ -888,10 +888,8 @@ class Assembler : public AssemblerBase { ...@@ -888,10 +888,8 @@ class Assembler : public AssemblerBase {
void mov_label_offset(Register dst, Label* label); void mov_label_offset(Register dst, Label* label);
// ARMv7 instructions for loading a 32 bit immediate in two instructions. // ARMv7 instructions for loading a 32 bit immediate in two instructions.
// This may actually emit a different mov instruction, but on an ARMv7 it // The constant for movw and movt should be in the range 0-0xffff.
// is guaranteed to only emit one instruction.
void movw(Register reg, uint32_t immediate, Condition cond = al); void movw(Register reg, uint32_t immediate, Condition cond = al);
// The constant for movt should be in the range 0-0xffff.
void movt(Register reg, uint32_t immediate, Condition cond = al); void movt(Register reg, uint32_t immediate, Condition cond = al);
void bic(Register dst, Register src1, const Operand& src2, void bic(Register dst, Register src1, const Operand& src2,
......
...@@ -841,7 +841,7 @@ void LCodeGen::DeoptimizeIf(Condition condition, ...@@ -841,7 +841,7 @@ void LCodeGen::DeoptimizeIf(Condition condition,
__ mov(scratch, Operand(count)); __ mov(scratch, Operand(count));
__ ldr(r1, MemOperand(scratch)); __ ldr(r1, MemOperand(scratch));
__ sub(r1, r1, Operand(1), SetCC); __ sub(r1, r1, Operand(1), SetCC);
__ movw(r1, FLAG_deopt_every_n_times, eq); __ mov(r1, Operand(FLAG_deopt_every_n_times), LeaveCC, eq);
__ str(r1, MemOperand(scratch)); __ str(r1, MemOperand(scratch));
__ pop(r1); __ pop(r1);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment