[riscv64] Fix codegen error of Simd128_AndNot

should using scratch register to hold intermediate result.

Change-Id: I08e2236fd0a491398ffaa15c4fd9ae3d0e9ef535
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3596441Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#80103}

src/compiler/backend/riscv64/code-generator-riscv64.cc

@@ -2074,9 +2074,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     }
     case kRiscvS128AndNot: {
       (__ VU).set(kScratchReg, VSew::E8, Vlmul::m1);
-      __ vnot_vv(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      __ vnot_vv(kSimd128ScratchReg, i.InputSimd128Register(1));
       __ vand_vv(i.OutputSimd128Register(), i.InputSimd128Register(0),
-                 i.OutputSimd128Register());
+                 kSimd128ScratchReg);
       break;
     }
     case kRiscvS128Const: {

src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h

@@ -2454,8 +2454,8 @@ void LiftoffAssembler::emit_s128_and_not(LiftoffRegister dst,
                                          LiftoffRegister lhs,
                                          LiftoffRegister rhs) {
   VU.set(kScratchReg, E8, m1);
-  vnot_vv(dst.fp().toV(), rhs.fp().toV());
-  vand_vv(dst.fp().toV(), lhs.fp().toV(), dst.fp().toV());
+  vnot_vv(kSimd128ScratchReg, rhs.fp().toV());
+  vand_vv(dst.fp().toV(), lhs.fp().toV(), kSimd128ScratchReg);
 }
 
 void LiftoffAssembler::emit_s128_select(LiftoffRegister dst,