Commit 79645fef authored by Ilija Pavlovic's avatar Ilija Pavlovic Committed by Commit Bot

MIPS: Prevent trampolines in LDC1 and SDC1.

Because of complexity macro instructions LDC1 and SDC1, which use
temporary registers on MIPS32, trampolines are prevented in these
instructions.

TEST=
BUG=

Change-Id: I40f50853f8dad195814007894ba1ad7c77c01892
Reviewed-on: https://chromium-review.googlesource.com/897422Reviewed-by: 's avatarIvica Bogosavljevic <ivica.bogosavljevic@mips.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Cr-Commit-Position: refs/heads/master@{#51021}
parent a3e20cf2
...@@ -1163,6 +1163,7 @@ void TurboAssembler::Usdc1(FPURegister fd, const MemOperand& rs, ...@@ -1163,6 +1163,7 @@ void TurboAssembler::Usdc1(FPURegister fd, const MemOperand& rs,
void TurboAssembler::Ldc1(FPURegister fd, const MemOperand& src) { void TurboAssembler::Ldc1(FPURegister fd, const MemOperand& src) {
// Workaround for non-8-byte alignment of HeapNumber, convert 64-bit // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
// load to two 32-bit loads. // load to two 32-bit loads.
BlockTrampolinePoolScope block_trampoline_pool(this);
DCHECK(Register::kMantissaOffset <= 4 && Register::kExponentOffset <= 4); DCHECK(Register::kMantissaOffset <= 4 && Register::kExponentOffset <= 4);
MemOperand tmp = src; MemOperand tmp = src;
AdjustBaseAndOffset(tmp, OffsetAccessType::TWO_ACCESSES); AdjustBaseAndOffset(tmp, OffsetAccessType::TWO_ACCESSES);
...@@ -1186,6 +1187,7 @@ void TurboAssembler::Ldc1(FPURegister fd, const MemOperand& src) { ...@@ -1186,6 +1187,7 @@ void TurboAssembler::Ldc1(FPURegister fd, const MemOperand& src) {
void TurboAssembler::Sdc1(FPURegister fd, const MemOperand& src) { void TurboAssembler::Sdc1(FPURegister fd, const MemOperand& src) {
// Workaround for non-8-byte alignment of HeapNumber, convert 64-bit // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
// store to two 32-bit stores. // store to two 32-bit stores.
BlockTrampolinePoolScope block_trampoline_pool(this);
DCHECK(Register::kMantissaOffset <= 4 && Register::kExponentOffset <= 4); DCHECK(Register::kMantissaOffset <= 4 && Register::kExponentOffset <= 4);
MemOperand tmp = src; MemOperand tmp = src;
AdjustBaseAndOffset(tmp, OffsetAccessType::TWO_ACCESSES); AdjustBaseAndOffset(tmp, OffsetAccessType::TWO_ACCESSES);
......
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