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Commit 76a60e15 authored by Zhao Jiazhong's avatar Zhao Jiazhong Committed by Commit Bot
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[mips][wasm-simd] Prototype f32x4 and f64x2 rounding 

Port ef1d6a3b
https://crrev.com/c/2227257

Change-Id: Id829db611fdfd475462efec2aa0ab6f94d3ddce3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2251680
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Reviewed-by: 's avatarDeepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#68625}
parent 83dddaca
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Showing with 205 additions and 9 deletions
src/codegen/mips64/assembler-mips64.cc
View file @ 76a60e15
...@@ -3596,7 +3596,7 @@ void Assembler::insve_d(MSARegister wd, uint32_t n, MSARegister ws) { ...@@ -3596,7 +3596,7 @@ void Assembler::insve_d(MSARegister wd, uint32_t n, MSARegister ws) {
} }
void Assembler::move_v(MSARegister wd, MSARegister ws) { void Assembler::move_v(MSARegister wd, MSARegister ws) {
DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); DCHECK(IsEnabled(MIPS_SIMD));
DCHECK(ws.is_valid() && wd.is_valid()); DCHECK(ws.is_valid() && wd.is_valid());
Instr instr = MSA | MOVE_V | (ws.code() << kWsShift) | Instr instr = MSA | MOVE_V | (ws.code() << kWsShift) |
(wd.code() << kWdShift) | MSA_ELM_MINOR; (wd.code() << kWdShift) | MSA_ELM_MINOR;
...@@ -3604,7 +3604,7 @@ void Assembler::move_v(MSARegister wd, MSARegister ws) { ...@@ -3604,7 +3604,7 @@ void Assembler::move_v(MSARegister wd, MSARegister ws) {
} }
void Assembler::ctcmsa(MSAControlRegister cd, Register rs) { void Assembler::ctcmsa(MSAControlRegister cd, Register rs) {
DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); DCHECK(IsEnabled(MIPS_SIMD));
DCHECK(cd.is_valid() && rs.is_valid()); DCHECK(cd.is_valid() && rs.is_valid());
Instr instr = MSA | CTCMSA | (rs.code() << kWsShift) | Instr instr = MSA | CTCMSA | (rs.code() << kWsShift) |
(cd.code() << kWdShift) | MSA_ELM_MINOR; (cd.code() << kWdShift) | MSA_ELM_MINOR;
...@@ -3612,7 +3612,7 @@ void Assembler::ctcmsa(MSAControlRegister cd, Register rs) { ...@@ -3612,7 +3612,7 @@ void Assembler::ctcmsa(MSAControlRegister cd, Register rs) {
} }
void Assembler::cfcmsa(Register rd, MSAControlRegister cs) { void Assembler::cfcmsa(Register rd, MSAControlRegister cs) {
DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); DCHECK(IsEnabled(MIPS_SIMD));
DCHECK(rd.is_valid() && cs.is_valid()); DCHECK(rd.is_valid() && cs.is_valid());
Instr instr = MSA | CFCMSA | (cs.code() << kWsShift) | Instr instr = MSA | CFCMSA | (cs.code() << kWsShift) |
(rd.code() << kWdShift) | MSA_ELM_MINOR; (rd.code() << kWdShift) | MSA_ELM_MINOR;
......
src/compiler/backend/instruction-selector.cc
View file @ 76a60e15
...@@ -2688,7 +2688,8 @@ void InstructionSelector::VisitF64x2Pmax(Node* node) { UNIMPLEMENTED(); } ...@@ -2688,7 +2688,8 @@ void InstructionSelector::VisitF64x2Pmax(Node* node) { UNIMPLEMENTED(); }
// !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64 // !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_S390X && \ #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_S390X && \
!V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64
// TODO(v8:10553) Prototyping floating point rounding instructions. // TODO(v8:10553) Prototyping floating point rounding instructions.
void InstructionSelector::VisitF64x2Ceil(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF64x2Ceil(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF64x2Floor(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF64x2Floor(Node* node) { UNIMPLEMENTED(); }
...@@ -2699,7 +2700,8 @@ void InstructionSelector::VisitF32x4Floor(Node* node) { UNIMPLEMENTED(); } ...@@ -2699,7 +2700,8 @@ void InstructionSelector::VisitF32x4Floor(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Trunc(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF32x4Trunc(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4NearestInt(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF32x4NearestInt(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_S390X #endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_S390X
// && !V8_TARGET_ARCH_IA32 // && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM &&
// !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM64 && \ #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM64 && \
!V8_TARGET_ARCH_ARM !V8_TARGET_ARCH_ARM
......
src/compiler/backend/mips/code-generator-mips.cc
View file @ 76a60e15
...@@ -2179,6 +2179,42 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2179,6 +2179,42 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ bsel_v(dst, lhs, rhs); __ bsel_v(dst, lhs, rhs);
break; break;
} }
case kMipsF64x2Ceil: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
__ li(kScratchReg2, kRoundToPlusInf);
__ ctcmsa(MSACSR, kScratchReg2);
__ frint_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMipsF64x2Floor: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
__ li(kScratchReg2, kRoundToMinusInf);
__ ctcmsa(MSACSR, kScratchReg2);
__ frint_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMipsF64x2Trunc: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
__ li(kScratchReg2, kRoundToZero);
__ ctcmsa(MSACSR, kScratchReg2);
__ frint_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMipsF64x2NearestInt: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
// kRoundToNearest == 0
__ ctcmsa(MSACSR, zero_reg);
__ frint_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMipsI64x2Add: { case kMipsI64x2Add: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ addv_d(i.OutputSimd128Register(), i.InputSimd128Register(0), __ addv_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
...@@ -2435,6 +2471,42 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2435,6 +2471,42 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ bsel_v(dst, lhs, rhs); __ bsel_v(dst, lhs, rhs);
break; break;
} }
case kMipsF32x4Ceil: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
__ li(kScratchReg2, kRoundToPlusInf);
__ ctcmsa(MSACSR, kScratchReg2);
__ frint_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMipsF32x4Floor: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
__ li(kScratchReg2, kRoundToMinusInf);
__ ctcmsa(MSACSR, kScratchReg2);
__ frint_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMipsF32x4Trunc: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
__ li(kScratchReg2, kRoundToZero);
__ ctcmsa(MSACSR, kScratchReg2);
__ frint_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMipsF32x4NearestInt: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
// kRoundToNearest == 0
__ ctcmsa(MSACSR, zero_reg);
__ frint_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMipsI32x4SConvertF32x4: { case kMipsI32x4SConvertF32x4: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ ftrunc_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0)); __ ftrunc_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
......
src/compiler/backend/mips/instruction-codes-mips.h
View file @ 76a60e15
...@@ -157,6 +157,10 @@ namespace compiler { ...@@ -157,6 +157,10 @@ namespace compiler {
V(MipsF64x2Le) \ V(MipsF64x2Le) \
V(MipsF64x2Pmin) \ V(MipsF64x2Pmin) \
V(MipsF64x2Pmax) \ V(MipsF64x2Pmax) \
V(MipsF64x2Ceil) \
V(MipsF64x2Floor) \
V(MipsF64x2Trunc) \
V(MipsF64x2NearestInt) \
V(MipsI64x2Add) \ V(MipsI64x2Add) \
V(MipsI64x2Sub) \ V(MipsI64x2Sub) \
V(MipsI64x2Mul) \ V(MipsI64x2Mul) \
...@@ -200,6 +204,10 @@ namespace compiler { ...@@ -200,6 +204,10 @@ namespace compiler {
V(MipsF32x4Le) \ V(MipsF32x4Le) \
V(MipsF32x4Pmin) \ V(MipsF32x4Pmin) \
V(MipsF32x4Pmax) \ V(MipsF32x4Pmax) \
V(MipsF32x4Ceil) \
V(MipsF32x4Floor) \
V(MipsF32x4Trunc) \
V(MipsF32x4NearestInt) \
V(MipsI32x4SConvertF32x4) \ V(MipsI32x4SConvertF32x4) \
V(MipsI32x4UConvertF32x4) \ V(MipsI32x4UConvertF32x4) \
V(MipsI32x4Neg) \ V(MipsI32x4Neg) \
......
src/compiler/backend/mips/instruction-scheduler-mips.cc
View file @ 76a60e15
...@@ -59,6 +59,10 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -59,6 +59,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsF64x2ReplaceLane: case kMipsF64x2ReplaceLane:
case kMipsF64x2Pmin: case kMipsF64x2Pmin:
case kMipsF64x2Pmax: case kMipsF64x2Pmax:
case kMipsF64x2Ceil:
case kMipsF64x2Floor:
case kMipsF64x2Trunc:
case kMipsF64x2NearestInt:
case kMipsI64x2Add: case kMipsI64x2Add:
case kMipsI64x2Sub: case kMipsI64x2Sub:
case kMipsI64x2Mul: case kMipsI64x2Mul:
...@@ -89,6 +93,10 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -89,6 +93,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsF32x4UConvertI32x4: case kMipsF32x4UConvertI32x4:
case kMipsF32x4Pmin: case kMipsF32x4Pmin:
case kMipsF32x4Pmax: case kMipsF32x4Pmax:
case kMipsF32x4Ceil:
case kMipsF32x4Floor:
case kMipsF32x4Trunc:
case kMipsF32x4NearestInt:
case kMipsFloat32Max: case kMipsFloat32Max:
case kMipsFloat32Min: case kMipsFloat32Min:
case kMipsFloat32RoundDown: case kMipsFloat32RoundDown:
......
src/compiler/backend/mips/instruction-selector-mips.cc
View file @ 76a60e15
...@@ -2101,6 +2101,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { ...@@ -2101,6 +2101,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F64x2Abs, kMipsF64x2Abs) \ V(F64x2Abs, kMipsF64x2Abs) \
V(F64x2Neg, kMipsF64x2Neg) \ V(F64x2Neg, kMipsF64x2Neg) \
V(F64x2Sqrt, kMipsF64x2Sqrt) \ V(F64x2Sqrt, kMipsF64x2Sqrt) \
V(F64x2Ceil, kMipsF64x2Ceil) \
V(F64x2Floor, kMipsF64x2Floor) \
V(F64x2Trunc, kMipsF64x2Trunc) \
V(F64x2NearestInt, kMipsF64x2NearestInt) \
V(I64x2Neg, kMipsI64x2Neg) \ V(I64x2Neg, kMipsI64x2Neg) \
V(F32x4SConvertI32x4, kMipsF32x4SConvertI32x4) \ V(F32x4SConvertI32x4, kMipsF32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMipsF32x4UConvertI32x4) \ V(F32x4UConvertI32x4, kMipsF32x4UConvertI32x4) \
...@@ -2109,6 +2113,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { ...@@ -2109,6 +2113,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F32x4Sqrt, kMipsF32x4Sqrt) \ V(F32x4Sqrt, kMipsF32x4Sqrt) \
V(F32x4RecipApprox, kMipsF32x4RecipApprox) \ V(F32x4RecipApprox, kMipsF32x4RecipApprox) \
V(F32x4RecipSqrtApprox, kMipsF32x4RecipSqrtApprox) \ V(F32x4RecipSqrtApprox, kMipsF32x4RecipSqrtApprox) \
V(F32x4Ceil, kMipsF32x4Ceil) \
V(F32x4Floor, kMipsF32x4Floor) \
V(F32x4Trunc, kMipsF32x4Trunc) \
V(F32x4NearestInt, kMipsF32x4NearestInt) \
V(I32x4SConvertF32x4, kMipsI32x4SConvertF32x4) \ V(I32x4SConvertF32x4, kMipsI32x4SConvertF32x4) \
V(I32x4UConvertF32x4, kMipsI32x4UConvertF32x4) \ V(I32x4UConvertF32x4, kMipsI32x4UConvertF32x4) \
V(I32x4Neg, kMipsI32x4Neg) \ V(I32x4Neg, kMipsI32x4Neg) \
......
src/compiler/backend/mips64/code-generator-mips64.cc
View file @ 76a60e15
...@@ -2285,6 +2285,42 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2285,6 +2285,42 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ bsel_v(dst, lhs, rhs); __ bsel_v(dst, lhs, rhs);
break; break;
} }
case kMips64F64x2Ceil: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
__ li(kScratchReg2, kRoundToPlusInf);
__ ctcmsa(MSACSR, kScratchReg2);
__ frint_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMips64F64x2Floor: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
__ li(kScratchReg2, kRoundToMinusInf);
__ ctcmsa(MSACSR, kScratchReg2);
__ frint_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMips64F64x2Trunc: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
__ li(kScratchReg2, kRoundToZero);
__ ctcmsa(MSACSR, kScratchReg2);
__ frint_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMips64F64x2NearestInt: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
// kRoundToNearest == 0
__ ctcmsa(MSACSR, zero_reg);
__ frint_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMips64I64x2ReplaceLane: { case kMips64I64x2ReplaceLane: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register src = i.InputSimd128Register(0); Simd128Register src = i.InputSimd128Register(0);
...@@ -2621,6 +2657,42 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2621,6 +2657,42 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ bsel_v(dst, lhs, rhs); __ bsel_v(dst, lhs, rhs);
break; break;
} }
case kMips64F32x4Ceil: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
__ li(kScratchReg2, kRoundToPlusInf);
__ ctcmsa(MSACSR, kScratchReg2);
__ frint_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMips64F32x4Floor: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
__ li(kScratchReg2, kRoundToMinusInf);
__ ctcmsa(MSACSR, kScratchReg2);
__ frint_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMips64F32x4Trunc: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
__ li(kScratchReg2, kRoundToZero);
__ ctcmsa(MSACSR, kScratchReg2);
__ frint_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMips64F32x4NearestInt: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ cfcmsa(kScratchReg, MSACSR);
// kRoundToNearest == 0
__ ctcmsa(MSACSR, zero_reg);
__ frint_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMips64I32x4SConvertF32x4: { case kMips64I32x4SConvertF32x4: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ ftrunc_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0)); __ ftrunc_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
......
src/compiler/backend/mips64/instruction-codes-mips64.h
View file @ 76a60e15
...@@ -205,6 +205,10 @@ namespace compiler { ...@@ -205,6 +205,10 @@ namespace compiler {
V(Mips64F64x2ReplaceLane) \ V(Mips64F64x2ReplaceLane) \
V(Mips64F64x2Pmin) \ V(Mips64F64x2Pmin) \
V(Mips64F64x2Pmax) \ V(Mips64F64x2Pmax) \
V(Mips64F64x2Ceil) \
V(Mips64F64x2Floor) \
V(Mips64F64x2Trunc) \
V(Mips64F64x2NearestInt) \
V(Mips64I64x2Splat) \ V(Mips64I64x2Splat) \
V(Mips64I64x2ExtractLane) \ V(Mips64I64x2ExtractLane) \
V(Mips64I64x2ReplaceLane) \ V(Mips64I64x2ReplaceLane) \
...@@ -233,6 +237,10 @@ namespace compiler { ...@@ -233,6 +237,10 @@ namespace compiler {
V(Mips64F32x4Le) \ V(Mips64F32x4Le) \
V(Mips64F32x4Pmin) \ V(Mips64F32x4Pmin) \
V(Mips64F32x4Pmax) \ V(Mips64F32x4Pmax) \
V(Mips64F32x4Ceil) \
V(Mips64F32x4Floor) \
V(Mips64F32x4Trunc) \
V(Mips64F32x4NearestInt) \
V(Mips64I32x4SConvertF32x4) \ V(Mips64I32x4SConvertF32x4) \
V(Mips64I32x4UConvertF32x4) \ V(Mips64I32x4UConvertF32x4) \
V(Mips64I32x4Neg) \ V(Mips64I32x4Neg) \
......
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
View file @ 76a60e15
...@@ -84,6 +84,10 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -84,6 +84,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64F64x2Le: case kMips64F64x2Le:
case kMips64F64x2Pmin: case kMips64F64x2Pmin:
case kMips64F64x2Pmax: case kMips64F64x2Pmax:
case kMips64F64x2Ceil:
case kMips64F64x2Floor:
case kMips64F64x2Trunc:
case kMips64F64x2NearestInt:
case kMips64I64x2Splat: case kMips64I64x2Splat:
case kMips64I64x2ExtractLane: case kMips64I64x2ExtractLane:
case kMips64I64x2ReplaceLane: case kMips64I64x2ReplaceLane:
...@@ -117,6 +121,10 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -117,6 +121,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64F32x4UConvertI32x4: case kMips64F32x4UConvertI32x4:
case kMips64F32x4Pmin: case kMips64F32x4Pmin:
case kMips64F32x4Pmax: case kMips64F32x4Pmax:
case kMips64F32x4Ceil:
case kMips64F32x4Floor:
case kMips64F32x4Trunc:
case kMips64F32x4NearestInt:
case kMips64F64x2Splat: case kMips64F64x2Splat:
case kMips64F64x2ExtractLane: case kMips64F64x2ExtractLane:
case kMips64F64x2ReplaceLane: case kMips64F64x2ReplaceLane:
......
src/compiler/backend/mips64/instruction-selector-mips64.cc
View file @ 76a60e15
...@@ -2774,6 +2774,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { ...@@ -2774,6 +2774,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F64x2Abs, kMips64F64x2Abs) \ V(F64x2Abs, kMips64F64x2Abs) \
V(F64x2Neg, kMips64F64x2Neg) \ V(F64x2Neg, kMips64F64x2Neg) \
V(F64x2Sqrt, kMips64F64x2Sqrt) \ V(F64x2Sqrt, kMips64F64x2Sqrt) \
V(F64x2Ceil, kMips64F64x2Ceil) \
V(F64x2Floor, kMips64F64x2Floor) \
V(F64x2Trunc, kMips64F64x2Trunc) \
V(F64x2NearestInt, kMips64F64x2NearestInt) \
V(I64x2Neg, kMips64I64x2Neg) \ V(I64x2Neg, kMips64I64x2Neg) \
V(F32x4SConvertI32x4, kMips64F32x4SConvertI32x4) \ V(F32x4SConvertI32x4, kMips64F32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMips64F32x4UConvertI32x4) \ V(F32x4UConvertI32x4, kMips64F32x4UConvertI32x4) \
...@@ -2782,6 +2786,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { ...@@ -2782,6 +2786,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F32x4Sqrt, kMips64F32x4Sqrt) \ V(F32x4Sqrt, kMips64F32x4Sqrt) \
V(F32x4RecipApprox, kMips64F32x4RecipApprox) \ V(F32x4RecipApprox, kMips64F32x4RecipApprox) \
V(F32x4RecipSqrtApprox, kMips64F32x4RecipSqrtApprox) \ V(F32x4RecipSqrtApprox, kMips64F32x4RecipSqrtApprox) \
V(F32x4Ceil, kMips64F32x4Ceil) \
V(F32x4Floor, kMips64F32x4Floor) \
V(F32x4Trunc, kMips64F32x4Trunc) \
V(F32x4NearestInt, kMips64F32x4NearestInt) \
V(I32x4SConvertF32x4, kMips64I32x4SConvertF32x4) \ V(I32x4SConvertF32x4, kMips64I32x4SConvertF32x4) \
V(I32x4UConvertF32x4, kMips64I32x4UConvertF32x4) \ V(I32x4UConvertF32x4, kMips64I32x4UConvertF32x4) \
V(I32x4Neg, kMips64I32x4Neg) \ V(I32x4Neg, kMips64I32x4Neg) \
......
test/cctest/wasm/test-run-wasm-simd.cc
View file @ 76a60e15
...@@ -692,7 +692,8 @@ WASM_SIMD_TEST(F32x4RecipSqrtApprox) { ...@@ -692,7 +692,8 @@ WASM_SIMD_TEST(F32x4RecipSqrtApprox) {
// TODO(v8:10553) Prototyping floating-point rounding instructions. // TODO(v8:10553) Prototyping floating-point rounding instructions.
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X || \ #if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X || \
V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_ARM V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64
WASM_SIMD_TEST_NO_LOWERING(F32x4Ceil) { WASM_SIMD_TEST_NO_LOWERING(F32x4Ceil) {
FLAG_SCOPE(wasm_simd_post_mvp); FLAG_SCOPE(wasm_simd_post_mvp);
RunF32x4UnOpTest(execution_tier, lower_simd, kExprF32x4Ceil, ceilf, true); RunF32x4UnOpTest(execution_tier, lower_simd, kExprF32x4Ceil, ceilf, true);
...@@ -714,7 +715,8 @@ WASM_SIMD_TEST_NO_LOWERING(F32x4NearestInt) { ...@@ -714,7 +715,8 @@ WASM_SIMD_TEST_NO_LOWERING(F32x4NearestInt) {
true); true);
} }
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X || #endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X ||
// V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_ARM // V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_MIPS ||
// V8_TARGET_ARCH_MIPS64
void RunF32x4BinOpTest(ExecutionTier execution_tier, LowerSimd lower_simd, void RunF32x4BinOpTest(ExecutionTier execution_tier, LowerSimd lower_simd,
WasmOpcode opcode, FloatBinOp expected_op) { WasmOpcode opcode, FloatBinOp expected_op) {
...@@ -1329,7 +1331,7 @@ WASM_SIMD_TEST_NO_LOWERING(F64x2Sqrt) { ...@@ -1329,7 +1331,7 @@ WASM_SIMD_TEST_NO_LOWERING(F64x2Sqrt) {
// TODO(v8:10553) Prototyping floating-point rounding instructions. // TODO(v8:10553) Prototyping floating-point rounding instructions.
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X || \ #if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X || \
V8_TARGET_ARCH_ARM V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_MIPS64
WASM_SIMD_TEST_NO_LOWERING(F64x2Ceil) { WASM_SIMD_TEST_NO_LOWERING(F64x2Ceil) {
FLAG_SCOPE(wasm_simd_post_mvp); FLAG_SCOPE(wasm_simd_post_mvp);
RunF64x2UnOpTest(execution_tier, lower_simd, kExprF64x2Ceil, ceil, true); RunF64x2UnOpTest(execution_tier, lower_simd, kExprF64x2Ceil, ceil, true);
...@@ -1351,7 +1353,7 @@ WASM_SIMD_TEST_NO_LOWERING(F64x2NearestInt) { ...@@ -1351,7 +1353,7 @@ WASM_SIMD_TEST_NO_LOWERING(F64x2NearestInt) {
true); true);
} }
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X || #endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X ||
// V8_TARGET_ARCH_ARM // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_MIPS64
void RunF64x2BinOpTest(ExecutionTier execution_tier, LowerSimd lower_simd, void RunF64x2BinOpTest(ExecutionTier execution_tier, LowerSimd lower_simd,
WasmOpcode opcode, DoubleBinOp expected_op) { WasmOpcode opcode, DoubleBinOp expected_op) {
......
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