Revert of MIPS64: Enable shorten-64-to-32 warning. (patchset #12 id:240001 of...

Revert of MIPS64: Enable shorten-64-to-32 warning. (patchset #12 id:240001 of https://codereview.chromium.org/1133163005/)

Reason for revert:
Compile failure: https://chromegw.corp.google.com/i/client.v8/builders/V8%20Mac64%20-%20debug/builds/3070/steps/compile/logs/stdio

Original issue's description:
> MIPS64: Enable shorten-64-to-32 warning.
>
> Port cdc43bc5
>
> Original commit message:
> Enable clang's shorten-64-to-32 warning flag on ARM64, and fix the warnings
> that arise.
>
> BUG=
>
> Committed: https://crrev.com/9af578a7c83b58a0ce25345998d9287cbf2030cb
> Cr-Commit-Position: refs/heads/master@{#28990}

TBR=danno@chromium.org,martyn.capewell@arm.com,paul.lind@imgtec.com,akos.palfi@imgtec.com,dusan.milosavljevic@imgtec.com,jkummerow@chromium.org,machenbach@chromium.org,svenpanne@chromium.org,balazs.kilvady@imgtec.com
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true
BUG=

Review URL: https://codereview.chromium.org/1182493007

Cr-Commit-Position: refs/heads/master@{#28991}

build/standalone.gypi

@@ -473,8 +473,7 @@
         ],
         'ldflags': [ '-pthread', ],
         'conditions': [
-          [ 'clang==1 and (v8_target_arch=="x64" or v8_target_arch=="arm64" \
-            or v8_target_arch=="mips64el")', {
+          [ 'clang==1 and (v8_target_arch=="x64" or v8_target_arch=="arm64")', {
             'cflags': [ '-Wshorten-64-to-32' ],
           }],
           [ 'host_arch=="ppc64" and OS!="aix"', {
@@ -658,12 +657,6 @@
               'GCC_VERSION': 'com.apple.compilers.llvm.clang.1_0',
               'CLANG_CXX_LANGUAGE_STANDARD': 'gnu++0x',  # -std=gnu++0x
             },
-            'conditions': [
-              ['v8_target_arch=="x64" or v8_target_arch=="arm64" \
-                or v8_target_arch=="mips64el"', {
-                'xcode_settings': {'WARNING_CFLAGS': ['-Wshorten-64-to-32']},
-              }],
-            ]
           }],
         ],
         'target_conditions': [

src/base/platform/time.cc

@@ -111,7 +111,7 @@ TimeDelta TimeDelta::FromMachTimespec(struct mach_timespec ts) {
 struct mach_timespec TimeDelta::ToMachTimespec() const {
   struct mach_timespec ts;
   DCHECK(delta_ >= 0);
-  ts.tv_sec = static_cast<unsigned>(delta_ / Time::kMicrosecondsPerSecond);
+  ts.tv_sec = delta_ / Time::kMicrosecondsPerSecond;
   ts.tv_nsec = (delta_ % Time::kMicrosecondsPerSecond) *
       Time::kNanosecondsPerMicrosecond;
   return ts;

src/compiler/mips64/code-generator-mips64.cc

@@ -310,7 +310,7 @@ FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
       __ Daddu(at, i.InputRegister(2), offset);                               \
       __ asm_instr(result, MemOperand(at, 0));                                \
     } else {                                                                  \
-      int offset = static_cast<int>(i.InputOperand(0).immediate());           \
+      auto offset = i.InputOperand(0).immediate();                            \
       __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset));       \
       __ asm_instr(result, MemOperand(i.InputRegister(2), offset));           \
     }                                                                         \
@@ -328,7 +328,7 @@ FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
       __ Daddu(at, i.InputRegister(2), offset);                               \
       __ asm_instr(result, MemOperand(at, 0));                                \
     } else {                                                                  \
-      int offset = static_cast<int>(i.InputOperand(0).immediate());           \
+      auto offset = i.InputOperand(0).immediate();                            \
       __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset));       \
       __ asm_instr(result, MemOperand(i.InputRegister(2), offset));           \
     }                                                                         \
@@ -346,7 +346,7 @@ FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
       __ Daddu(at, i.InputRegister(3), offset);                        \
       __ asm_instr(value, MemOperand(at, 0));                          \
     } else {                                                           \
-      int offset = static_cast<int>(i.InputOperand(0).immediate());    \
+      auto offset = i.InputOperand(0).immediate();                     \
       auto value = i.Input##width##Register(2);                        \
       __ Branch(&done, ls, i.InputRegister(1), Operand(offset));       \
       __ asm_instr(value, MemOperand(i.InputRegister(3), offset));     \
@@ -365,7 +365,7 @@ FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
       __ Daddu(at, i.InputRegister(3), offset);                        \
       __ asm_instr(value, MemOperand(at, 0));                          \
     } else {                                                           \
-      int offset = static_cast<int>(i.InputOperand(0).immediate());    \
+      auto offset = i.InputOperand(0).immediate();                     \
       auto value = i.InputRegister(2);                                 \
       __ Branch(&done, ls, i.InputRegister(1), Operand(offset));       \
       __ asm_instr(value, MemOperand(i.InputRegister(3), offset));     \
@@ -559,27 +559,24 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       if (instr->InputAt(1)->IsRegister()) {
         __ sllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
-        int64_t imm = i.InputOperand(1).immediate();
-        __ sll(i.OutputRegister(), i.InputRegister(0),
-               static_cast<uint16_t>(imm));
+        int32_t imm = i.InputOperand(1).immediate();
+        __ sll(i.OutputRegister(), i.InputRegister(0), imm);
       }
       break;
     case kMips64Shr:
       if (instr->InputAt(1)->IsRegister()) {
         __ srlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
-        int64_t imm = i.InputOperand(1).immediate();
-        __ srl(i.OutputRegister(), i.InputRegister(0),
-               static_cast<uint16_t>(imm));
+        int32_t imm = i.InputOperand(1).immediate();
+        __ srl(i.OutputRegister(), i.InputRegister(0), imm);
       }
       break;
     case kMips64Sar:
       if (instr->InputAt(1)->IsRegister()) {
         __ srav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
-        int64_t imm = i.InputOperand(1).immediate();
-        __ sra(i.OutputRegister(), i.InputRegister(0),
-               static_cast<uint16_t>(imm));
+        int32_t imm = i.InputOperand(1).immediate();
+        __ sra(i.OutputRegister(), i.InputRegister(0), imm);
       }
       break;
     case kMips64Ext:
@@ -594,13 +591,11 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       if (instr->InputAt(1)->IsRegister()) {
         __ dsllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
-        int64_t imm = i.InputOperand(1).immediate();
+        int32_t imm = i.InputOperand(1).immediate();
         if (imm < 32) {
-          __ dsll(i.OutputRegister(), i.InputRegister(0),
-                  static_cast<uint16_t>(imm));
+          __ dsll(i.OutputRegister(), i.InputRegister(0), imm);
         } else {
-          __ dsll32(i.OutputRegister(), i.InputRegister(0),
-                    static_cast<uint16_t>(imm - 32));
+          __ dsll32(i.OutputRegister(), i.InputRegister(0), imm - 32);
         }
       }
       break;
@@ -608,13 +603,11 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       if (instr->InputAt(1)->IsRegister()) {
         __ dsrlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
-        int64_t imm = i.InputOperand(1).immediate();
+        int32_t imm = i.InputOperand(1).immediate();
         if (imm < 32) {
-          __ dsrl(i.OutputRegister(), i.InputRegister(0),
-                  static_cast<uint16_t>(imm));
+          __ dsrl(i.OutputRegister(), i.InputRegister(0), imm);
         } else {
-          __ dsrl32(i.OutputRegister(), i.InputRegister(0),
-                    static_cast<uint16_t>(imm - 32));
+          __ dsrl32(i.OutputRegister(), i.InputRegister(0), imm - 32);
         }
       }
       break;
@@ -622,7 +615,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       if (instr->InputAt(1)->IsRegister()) {
         __ dsrav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
-        int64_t imm = i.InputOperand(1).immediate();
+        int32_t imm = i.InputOperand(1).immediate();
         if (imm < 32) {
           __ dsra(i.OutputRegister(), i.InputRegister(0), imm);
         } else {
@@ -1103,7 +1096,7 @@ void CodeGenerator::AssembleArchTableSwitch(Instruction* instr) {
   Label here;
 
   __ Branch(GetLabel(i.InputRpo(1)), hs, input, Operand(case_count));
-  __ BlockTrampolinePoolFor(static_cast<int>(case_count) * 2 + 7);
+  __ BlockTrampolinePoolFor(case_count * 2 + 7);
   // Ensure that dd-ed labels use 8 byte aligned addresses.
   if ((masm()->pc_offset() & 7) != 0) {
     __ nop();

src/compiler/mips64/instruction-selector-mips64.cc

@@ -393,7 +393,7 @@ void InstructionSelector::VisitInt64Mul(Node* node) {
   Int64BinopMatcher m(node);
   // TODO(dusmil): Add optimization for shifts larger than 32.
   if (m.right().HasValue() && m.right().Value() > 0) {
-    int32_t value = static_cast<int32_t>(m.right().Value());
+    int64_t value = m.right().Value();
     if (base::bits::IsPowerOfTwo32(value)) {
       Emit(kMips64Dshl | AddressingModeField::encode(kMode_None),
            g.DefineAsRegister(node), g.UseRegister(m.left().node()),
@@ -666,8 +666,8 @@ void InstructionSelector::VisitCall(Node* node, BasicBlock* handler) {
 
   FrameStateDescriptor* frame_state_descriptor = nullptr;
   if (descriptor->NeedsFrameState()) {
-    frame_state_descriptor = GetFrameStateDescriptor(
-        node->InputAt(static_cast<int>(descriptor->InputCount())));
+    frame_state_descriptor =
+        GetFrameStateDescriptor(node->InputAt(descriptor->InputCount()));
   }
 
   CallBuffer buffer(zone(), descriptor, frame_state_descriptor);
@@ -675,12 +675,12 @@ void InstructionSelector::VisitCall(Node* node, BasicBlock* handler) {
   // Compute InstructionOperands for inputs and outputs.
   InitializeCallBuffer(node, &buffer, true, false);
 
-  const int32_t push_count = static_cast<int32_t>(buffer.pushed_nodes.size());
+  int push_count = buffer.pushed_nodes.size();
   if (push_count > 0) {
     Emit(kMips64StackClaim, g.NoOutput(),
          g.TempImmediate(push_count << kPointerSizeLog2));
   }
-  int32_t slot = push_count - 1;
+  int slot = buffer.pushed_nodes.size() - 1;
   for (Node* node : base::Reversed(buffer.pushed_nodes)) {
     Emit(kMips64StoreToStackSlot, g.NoOutput(), g.UseRegister(node),
          g.TempImmediate(slot << kPointerSizeLog2));
@@ -771,12 +771,12 @@ void InstructionSelector::VisitTailCall(Node* node) {
     // Compute InstructionOperands for inputs and outputs.
     InitializeCallBuffer(node, &buffer, true, false);
 
-    const int32_t push_count = static_cast<int32_t>(buffer.pushed_nodes.size());
+    int push_count = buffer.pushed_nodes.size();
     if (push_count > 0) {
       Emit(kMips64StackClaim, g.NoOutput(),
            g.TempImmediate(push_count << kPointerSizeLog2));
     }
-    int slot = push_count - 1;
+    int slot = buffer.pushed_nodes.size() - 1;
     for (Node* node : base::Reversed(buffer.pushed_nodes)) {
       Emit(kMips64StoreToStackSlot, g.NoOutput(), g.UseRegister(node),
            g.TempImmediate(slot << kPointerSizeLog2));

src/ic/mips64/stub-cache-mips64.cc

@@ -57,16 +57,14 @@ static void ProbeTable(Isolate* isolate, MacroAssembler* masm,
   __ Branch(&miss, ne, name, Operand(at));
 
   // Check the map matches.
-  __ ld(at, MemOperand(base_addr,
-                       static_cast<int32_t>(map_off_addr - key_off_addr)));
+  __ ld(at, MemOperand(base_addr, map_off_addr - key_off_addr));
   __ ld(scratch2, FieldMemOperand(receiver, HeapObject::kMapOffset));
   __ Branch(&miss, ne, at, Operand(scratch2));
 
   // Get the code entry from the cache.
   Register code = scratch2;
   scratch2 = no_reg;
-  __ ld(code, MemOperand(base_addr,
-                         static_cast<int32_t>(value_off_addr - key_off_addr)));
+  __ ld(code, MemOperand(base_addr, value_off_addr - key_off_addr));
 
   // Check that the flags match what we're looking for.
   Register flags_reg = base_addr;

src/mips64/assembler-mips64.cc

@@ -211,14 +211,13 @@ Operand::Operand(Handle<Object> handle) {
 }
 
 
-MemOperand::MemOperand(Register rm, int32_t offset) : Operand(rm) {
+MemOperand::MemOperand(Register rm, int64_t offset) : Operand(rm) {
   offset_ = offset;
 }
 
 
-MemOperand::MemOperand(Register rm, int32_t unit, int32_t multiplier,
-                       OffsetAddend offset_addend)
-    : Operand(rm) {
+MemOperand::MemOperand(Register rm, int64_t unit, int64_t multiplier,
+                       OffsetAddend offset_addend) : Operand(rm) {
   offset_ = unit * multiplier + offset_addend;
 }
 
@@ -291,8 +290,7 @@ void Assembler::GetCode(CodeDesc* desc) {
   desc->buffer = buffer_;
   desc->buffer_size = buffer_size_;
   desc->instr_size = pc_offset();
-  desc->reloc_size =
-      static_cast<int>((buffer_ + buffer_size_) - reloc_info_writer.pos());
+  desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
   desc->origin = this;
 }
 
@@ -743,7 +741,7 @@ void Assembler::target_at_put(int pos, int target_pos, bool is_internal) {
     DCHECK((imm28 & 3) == 0);
 
     instr &= ~kImm26Mask;
-    uint32_t imm26 = static_cast<uint32_t>(imm28 >> 2);
+    uint32_t imm26 = imm28 >> 2;
     DCHECK(is_uint26(imm26));
 
     instr_at_put(pos, instr | (imm26 & kImm26Mask));
@@ -1387,7 +1385,7 @@ void Assembler::j(int64_t target) {
     DCHECK(in_range && ((target & 3) == 0));
   }
 #endif
-  GenInstrJump(J, static_cast<uint32_t>(target >> 2) & kImm26Mask);
+  GenInstrJump(J, (target >> 2) & kImm26Mask);
 }
 
 
@@ -1416,7 +1414,7 @@ void Assembler::jal(int64_t target) {
   }
 #endif
   positions_recorder()->WriteRecordedPositions();
-  GenInstrJump(JAL, static_cast<uint32_t>(target >> 2) & kImm26Mask);
+  GenInstrJump(JAL, (target >> 2) & kImm26Mask);
 }
 
 
@@ -2903,8 +2901,7 @@ void Assembler::GrowBuffer() {
   desc.buffer = NewArray<byte>(desc.buffer_size);
 
   desc.instr_size = pc_offset();
-  desc.reloc_size =
-      static_cast<int>((buffer_ + buffer_size_) - reloc_info_writer.pos());
+  desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
 
   // Copy the data.
   intptr_t pc_delta = desc.buffer - buffer_;

src/mips64/assembler-mips64.h

@@ -404,8 +404,8 @@ class MemOperand : public Operand {
     offset_zero = 0
   };
 
-  explicit MemOperand(Register rn, int32_t offset = 0);
-  explicit MemOperand(Register rn, int32_t unit, int32_t multiplier,
+  explicit MemOperand(Register rn, int64_t offset = 0);
+  explicit MemOperand(Register rn, int64_t unit, int64_t multiplier,
                       OffsetAddend offset_addend = offset_zero);
   int32_t offset() const { return offset_; }
 
@@ -1138,9 +1138,7 @@ class Assembler : public AssemblerBase {
   inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; }
 
   // Get the number of bytes available in the buffer.
-  inline intptr_t available_space() const {
-    return reloc_info_writer.pos() - pc_;
-  }
+  inline int available_space() const { return reloc_info_writer.pos() - pc_; }
 
   // Read/patch instructions.
   static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); }

src/mips64/disasm-mips64.cc

@@ -272,7 +272,7 @@ void Decoder::PrintXImm21(Instruction* instr) {
 
 // Print 26-bit immediate value.
 void Decoder::PrintXImm26(Instruction* instr) {
-  uint32_t imm = static_cast<uint32_t>(instr->Imm26Value()) << kImmFieldShift;
+  uint32_t imm = instr->Imm26Value() << kImmFieldShift;
   out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
 }
 

src/mips64/lithium-codegen-mips64.cc

@@ -489,7 +489,7 @@ int32_t LCodeGen::ToInteger32(LConstantOperand* op) const {
 }
 
 
-int64_t LCodeGen::ToRepresentation_donotuse(LConstantOperand* op,
+int32_t LCodeGen::ToRepresentation_donotuse(LConstantOperand* op,
                                    const Representation& r) const {
   HConstant* constant = chunk_->LookupConstant(op);
   int32_t value = constant->Integer32Value();

src/mips64/lithium-codegen-mips64.h

@@ -75,7 +75,7 @@ class LCodeGen: public LCodeGenBase {
   DoubleRegister EmitLoadDoubleRegister(LOperand* op,
                                         FloatRegister flt_scratch,
                                         DoubleRegister dbl_scratch);
-  int64_t ToRepresentation_donotuse(LConstantOperand* op,
+  int32_t ToRepresentation_donotuse(LConstantOperand* op,
                                     const Representation& r) const;
   int32_t ToInteger32(LConstantOperand* op) const;
   Smi* ToSmi(LConstantOperand* op) const;

src/mips64/simulator-mips64.h

@@ -326,55 +326,57 @@ class Simulator {
   inline int32_t SetDoubleLOW(double* addr);
 
   // functions called from DecodeTypeRegister
-  void DecodeTypeRegisterCOP1(Instruction* instr, const int32_t rs_reg,
-                              const int64_t rs, const uint64_t rs_u,
-                              const int32_t rt_reg, const int64_t rt,
-                              const uint64_t rt_u, const int32_t rd_reg,
-                              const int32_t fr_reg, const int32_t fs_reg,
-                              const int32_t ft_reg, const int32_t fd_reg,
+  void DecodeTypeRegisterCOP1(Instruction* instr, const int32_t& rs_reg,
+                              const int64_t& rs, const uint64_t& rs_u,
+                              const int32_t& rt_reg, const int64_t& rt,
+                              const uint64_t& rt_u, const int32_t& rd_reg,
+                              const int32_t& fr_reg, const int32_t& fs_reg,
+                              const int32_t& ft_reg, const int32_t& fd_reg,
                               int64_t& alu_out);
 
-  void DecodeTypeRegisterCOP1X(Instruction* instr, const int32_t fr_reg,
-                               const int32_t fs_reg, const int32_t ft_reg,
-                               const int32_t fd_reg);
+  void DecodeTypeRegisterCOP1X(Instruction* instr, const int32_t& fr_reg,
+                               const int32_t& fs_reg, const int32_t& ft_reg,
+                               const int32_t& fd_reg);
 
   void DecodeTypeRegisterSPECIAL(
-      Instruction* instr, const int32_t rs_reg, const int64_t rs,
-      const uint64_t rs_u, const int32_t rt_reg, const int64_t rt,
-      const uint64_t rt_u, const int32_t rd_reg, const int32_t fr_reg,
-      const int32_t fs_reg, const int32_t ft_reg, const int32_t fd_reg,
-      const int64_t i64hilo, const uint64_t u64hilo, const int64_t alu_out,
-      const bool do_interrupt, const int64_t current_pc, const int64_t next_pc,
-      const int32_t return_addr_reg, const int64_t i128resultH,
-      const int64_t i128resultL);
-
-
-  void DecodeTypeRegisterSPECIAL2(Instruction* instr, const int32_t rd_reg,
-                                  const int64_t alu_out);
+      Instruction* instr, const int64_t& rs_reg, const int64_t& rs,
+      const uint64_t& rs_u, const int64_t& rt_reg, const int64_t& rt,
+      const uint64_t& rt_u, const int64_t& rd_reg, const int32_t& fr_reg,
+      const int32_t& fs_reg, const int32_t& ft_reg, const int64_t& fd_reg,
+      int64_t& i64hilo, uint64_t& u64hilo, int64_t& alu_out, bool& do_interrupt,
+      int64_t& current_pc, int64_t& next_pc, int64_t& return_addr_reg,
+      int64_t& i128resultH, int64_t& i128resultL);
+
+  void DecodeTypeRegisterSPECIAL2(Instruction* instr, const int64_t& rd_reg,
+                                  int64_t& alu_out);
 
-  void DecodeTypeRegisterSPECIAL3(Instruction* instr, const int32_t rt_reg,
-                                  const int32_t rd_reg, const int64_t alu_out);
+  void DecodeTypeRegisterSPECIAL3(Instruction* instr, const int64_t& rt_reg,
+                                  const int64_t& rd_reg, int64_t& alu_out);
 
-  void DecodeTypeRegisterSRsType(Instruction* instr, const int32_t fs_reg,
-                                 const int32_t ft_reg, const int32_t fd_reg);
+  void DecodeTypeRegisterSRsType(Instruction* instr, const int32_t& fs_reg,
+                                 const int32_t& ft_reg, const int32_t& fd_reg);
 
-  void DecodeTypeRegisterDRsType(Instruction* instr, const int32_t fs_reg,
-                                 const int32_t ft_reg, const int32_t fd_reg);
+  void DecodeTypeRegisterDRsType(Instruction* instr, const int32_t& fs_reg,
+                                 const int32_t& ft_reg, const int32_t& fd_reg);
 
-  void DecodeTypeRegisterWRsType(Instruction* instr, const int32_t fs_reg,
-                                 const int32_t ft_reg, const int32_t fd_reg,
+  void DecodeTypeRegisterWRsType(Instruction* instr, const int32_t& fs_reg,
+                                 const int32_t& ft_reg, const int32_t& fd_reg,
                                  int64_t& alu_out);
 
-  void DecodeTypeRegisterLRsType(Instruction* instr, const int32_t fs_reg,
-                                 const int32_t fd_reg, const int32_t ft_reg);
+  void DecodeTypeRegisterLRsType(Instruction* instr, const int32_t& fs_reg,
+                                 const int32_t& fd_reg, const int32_t& ft_reg);
   // Executing is handled based on the instruction type.
   void DecodeTypeRegister(Instruction* instr);
 
   // Helper function for DecodeTypeRegister.
-  void ConfigureTypeRegister(Instruction* instr, int64_t* alu_out,
-                             int64_t* i64hilo, uint64_t* u64hilo,
-                             int64_t* next_pc, int* return_addr_reg,
-                             bool* do_interrupt, int64_t* result128H,
+  void ConfigureTypeRegister(Instruction* instr,
+                             int64_t* alu_out,
+                             int64_t* i64hilo,
+                             uint64_t* u64hilo,
+                             int64_t* next_pc,
+                             int64_t* return_addr_reg,
+                             bool* do_interrupt,
+                             int64_t* result128H,
                              int64_t* result128L);
 
   void DecodeTypeImmediate(Instruction* instr);
@@ -416,7 +418,7 @@ class Simulator {
   // ICache.
   static void CheckICache(v8::internal::HashMap* i_cache, Instruction* instr);
   static void FlushOnePage(v8::internal::HashMap* i_cache, intptr_t start,
-                           size_t size);
+                           int size);
   static CachePage* GetCachePage(v8::internal::HashMap* i_cache, void* page);
 
   enum Exception {
@@ -496,14 +498,12 @@ class Simulator {
 
 #ifdef MIPS_ABI_N64
 #define CALL_GENERATED_REGEXP_CODE(entry, p0, p1, p2, p3, p4, p5, p6, p7, p8) \
-  static_cast<int>(                                                           \
-      Simulator::current(Isolate::Current())                                  \
-          ->Call(entry, 10, p0, p1, p2, p3, p4, p5, p6, p7, NULL, p8))
+    Simulator::current(Isolate::Current())->Call( \
+        entry, 10, p0, p1, p2, p3, p4, p5, p6, p7, NULL, p8)
 #else  // Must be O32 Abi.
 #define CALL_GENERATED_REGEXP_CODE(entry, p0, p1, p2, p3, p4, p5, p6, p7, p8) \
-  static_cast<int>(                                                           \
-      Simulator::current(Isolate::Current())                                  \
-          ->Call(entry, 10, p0, p1, p2, p3, NULL, p4, p5, p6, p7, p8))
+    Simulator::current(Isolate::Current())->Call( \
+        entry, 10, p0, p1, p2, p3, NULL, p4, p5, p6, p7, p8)
 #endif  // MIPS_ABI_N64
 
 

test/cctest/test-assembler-mips64.cc

@@ -3121,9 +3121,8 @@ TEST(jump_tables1) {
 #endif
   F1 f = FUNCTION_CAST<F1>(code->entry());
   for (int i = 0; i < kNumCases; ++i) {
-    int64_t res = reinterpret_cast<int64_t>(
-        CALL_GENERATED_CODE(f, i, 0, 0, 0, 0));
-    ::printf("f(%d) = %" PRId64 "\n", i, res);
+    int res = reinterpret_cast<int64_t>(CALL_GENERATED_CODE(f, i, 0, 0, 0, 0));
+    ::printf("f(%d) = %d\n", i, res);
     CHECK_EQ(values[i], static_cast<int>(res));
   }
 }
@@ -3193,9 +3192,8 @@ TEST(jump_tables2) {
 #endif
   F1 f = FUNCTION_CAST<F1>(code->entry());
   for (int i = 0; i < kNumCases; ++i) {
-    int64_t res = reinterpret_cast<int64_t>(
-        CALL_GENERATED_CODE(f, i, 0, 0, 0, 0));
-    ::printf("f(%d) = %" PRId64 "\n", i, res);
+    int res = reinterpret_cast<int64_t>(CALL_GENERATED_CODE(f, i, 0, 0, 0, 0));
+    ::printf("f(%d) = %d\n", i, res);
     CHECK_EQ(values[i], res);
   }
 }

test/cctest/test-code-stubs-mips64.cc

@@ -144,8 +144,7 @@ int32_t RunGeneratedCodeCallWrapper(ConvertDToIFunc func,
                                     double from) {
 #ifdef USE_SIMULATOR
   Simulator::current(Isolate::Current())->CallFP(FUNCTION_ADDR(func), from, 0.);
-  return static_cast<int32_t>(
-      Simulator::current(Isolate::Current())->get_register(v0.code()));
+  return Simulator::current(Isolate::Current())->get_register(v0.code());
 #else
   return (*func)(from);
 #endif