Revert of MIPS64: Enable shorten-64-to-32 warning. (patchset #12 id:240001 of...

Revert of MIPS64: Enable shorten-64-to-32 warning. (patchset #12 id:240001 of https://codereview.chromium.org/1133163005/)

Reason for revert:
Compile failure: https://chromegw.corp.google.com/i/client.v8/builders/V8%20Mac64%20-%20debug/builds/3070/steps/compile/logs/stdio

Original issue's description:
> MIPS64: Enable shorten-64-to-32 warning.
>
> Port cdc43bc5
>
> Original commit message:
> Enable clang's shorten-64-to-32 warning flag on ARM64, and fix the warnings
> that arise.
>
> BUG=
>
> Committed: https://crrev.com/9af578a7c83b58a0ce25345998d9287cbf2030cb
> Cr-Commit-Position: refs/heads/master@{#28990}

TBR=danno@chromium.org,martyn.capewell@arm.com,paul.lind@imgtec.com,akos.palfi@imgtec.com,dusan.milosavljevic@imgtec.com,jkummerow@chromium.org,machenbach@chromium.org,svenpanne@chromium.org,balazs.kilvady@imgtec.com
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true
BUG=

Review URL: https://codereview.chromium.org/1182493007

Cr-Commit-Position: refs/heads/master@{#28991}

build/standalone.gypi

@@ -473,8 +473,7 @@
         ],
         'ldflags': [ '-pthread', ],
         'conditions': [
-          [ 'clang==1 and (v8_target_arch=="x64" or v8_target_arch=="arm64" \
-            or v8_target_arch=="mips64el")', {
+          [ 'clang==1 and (v8_target_arch=="x64" or v8_target_arch=="arm64")', {
             'cflags': [ '-Wshorten-64-to-32' ],
           }],
           [ 'host_arch=="ppc64" and OS!="aix"', {
@@ -658,12 +657,6 @@
               'GCC_VERSION': 'com.apple.compilers.llvm.clang.1_0',
               'CLANG_CXX_LANGUAGE_STANDARD': 'gnu++0x',  # -std=gnu++0x
             },
-            'conditions': [
-              ['v8_target_arch=="x64" or v8_target_arch=="arm64" \
-                or v8_target_arch=="mips64el"', {
-                'xcode_settings': {'WARNING_CFLAGS': ['-Wshorten-64-to-32']},
-              }],
-            ]
           }],
         ],
         'target_conditions': [

src/base/platform/time.cc

@@ -111,7 +111,7 @@ TimeDelta TimeDelta::FromMachTimespec(struct mach_timespec ts) {
 struct mach_timespec TimeDelta::ToMachTimespec() const {
   struct mach_timespec ts;
   DCHECK(delta_ >= 0);
-  ts.tv_sec = static_cast<unsigned>(delta_ / Time::kMicrosecondsPerSecond);
+  ts.tv_sec = delta_ / Time::kMicrosecondsPerSecond;
   ts.tv_nsec = (delta_ % Time::kMicrosecondsPerSecond) *
       Time::kNanosecondsPerMicrosecond;
   return ts;

src/compiler/mips64/code-generator-mips64.cc

@@ -310,7 +310,7 @@ FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
       __ Daddu(at, i.InputRegister(2), offset);                               \
       __ asm_instr(result, MemOperand(at, 0));                                \
     } else {                                                                  \
-      int offset = static_cast<int>(i.InputOperand(0).immediate());           \
+      auto offset = i.InputOperand(0).immediate();                            \
       __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset));       \
       __ asm_instr(result, MemOperand(i.InputRegister(2), offset));           \
     }                                                                         \
@@ -328,7 +328,7 @@ FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
       __ Daddu(at, i.InputRegister(2), offset);                               \
       __ asm_instr(result, MemOperand(at, 0));                                \
     } else {                                                                  \
-      int offset = static_cast<int>(i.InputOperand(0).immediate());           \
+      auto offset = i.InputOperand(0).immediate();                            \
       __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset));       \
       __ asm_instr(result, MemOperand(i.InputRegister(2), offset));           \
     }                                                                         \
@@ -346,7 +346,7 @@ FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
       __ Daddu(at, i.InputRegister(3), offset);                        \
       __ asm_instr(value, MemOperand(at, 0));                          \
     } else {                                                           \
-      int offset = static_cast<int>(i.InputOperand(0).immediate());    \
+      auto offset = i.InputOperand(0).immediate();                     \
       auto value = i.Input##width##Register(2);                        \
       __ Branch(&done, ls, i.InputRegister(1), Operand(offset));       \
       __ asm_instr(value, MemOperand(i.InputRegister(3), offset));     \
@@ -365,7 +365,7 @@ FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
       __ Daddu(at, i.InputRegister(3), offset);                        \
       __ asm_instr(value, MemOperand(at, 0));                          \
     } else {                                                           \
-      int offset = static_cast<int>(i.InputOperand(0).immediate());    \
+      auto offset = i.InputOperand(0).immediate();                     \
       auto value = i.InputRegister(2);                                 \
       __ Branch(&done, ls, i.InputRegister(1), Operand(offset));       \
       __ asm_instr(value, MemOperand(i.InputRegister(3), offset));     \
@@ -559,27 +559,24 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       if (instr->InputAt(1)->IsRegister()) {
         __ sllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
-        int64_t imm = i.InputOperand(1).immediate();
-        __ sll(i.OutputRegister(), i.InputRegister(0),
-               static_cast<uint16_t>(imm));
+        int32_t imm = i.InputOperand(1).immediate();
+        __ sll(i.OutputRegister(), i.InputRegister(0), imm);
       }
       break;
     case kMips64Shr:
       if (instr->InputAt(1)->IsRegister()) {
         __ srlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
-        int64_t imm = i.InputOperand(1).immediate();
-        __ srl(i.OutputRegister(), i.InputRegister(0),
-               static_cast<uint16_t>(imm));
+        int32_t imm = i.InputOperand(1).immediate();
+        __ srl(i.OutputRegister(), i.InputRegister(0), imm);
       }
       break;
     case kMips64Sar:
       if (instr->InputAt(1)->IsRegister()) {
         __ srav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
-        int64_t imm = i.InputOperand(1).immediate();
-        __ sra(i.OutputRegister(), i.InputRegister(0),
-               static_cast<uint16_t>(imm));
+        int32_t imm = i.InputOperand(1).immediate();
+        __ sra(i.OutputRegister(), i.InputRegister(0), imm);
       }
       break;
     case kMips64Ext:
@@ -594,13 +591,11 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       if (instr->InputAt(1)->IsRegister()) {
         __ dsllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
-        int64_t imm = i.InputOperand(1).immediate();
+        int32_t imm = i.InputOperand(1).immediate();
         if (imm < 32) {
-          __ dsll(i.OutputRegister(), i.InputRegister(0),
-                  static_cast<uint16_t>(imm));
+          __ dsll(i.OutputRegister(), i.InputRegister(0), imm);
         } else {
-          __ dsll32(i.OutputRegister(), i.InputRegister(0),
-                    static_cast<uint16_t>(imm - 32));
+          __ dsll32(i.OutputRegister(), i.InputRegister(0), imm - 32);
         }
       }
       break;
@@ -608,13 +603,11 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       if (instr->InputAt(1)->IsRegister()) {
         __ dsrlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
-        int64_t imm = i.InputOperand(1).immediate();
+        int32_t imm = i.InputOperand(1).immediate();
         if (imm < 32) {
-          __ dsrl(i.OutputRegister(), i.InputRegister(0),
-                  static_cast<uint16_t>(imm));
+          __ dsrl(i.OutputRegister(), i.InputRegister(0), imm);
         } else {
-          __ dsrl32(i.OutputRegister(), i.InputRegister(0),
-                    static_cast<uint16_t>(imm - 32));
+          __ dsrl32(i.OutputRegister(), i.InputRegister(0), imm - 32);
         }
       }
       break;
@@ -622,7 +615,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       if (instr->InputAt(1)->IsRegister()) {
         __ dsrav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
-        int64_t imm = i.InputOperand(1).immediate();
+        int32_t imm = i.InputOperand(1).immediate();
         if (imm < 32) {
           __ dsra(i.OutputRegister(), i.InputRegister(0), imm);
         } else {
@@ -1103,7 +1096,7 @@ void CodeGenerator::AssembleArchTableSwitch(Instruction* instr) {
   Label here;
 
   __ Branch(GetLabel(i.InputRpo(1)), hs, input, Operand(case_count));
-  __ BlockTrampolinePoolFor(static_cast<int>(case_count) * 2 + 7);
+  __ BlockTrampolinePoolFor(case_count * 2 + 7);
   // Ensure that dd-ed labels use 8 byte aligned addresses.
   if ((masm()->pc_offset() & 7) != 0) {
     __ nop();

src/compiler/mips64/instruction-selector-mips64.cc

@@ -393,7 +393,7 @@ void InstructionSelector::VisitInt64Mul(Node* node) {
   Int64BinopMatcher m(node);
   // TODO(dusmil): Add optimization for shifts larger than 32.
   if (m.right().HasValue() && m.right().Value() > 0) {
-    int32_t value = static_cast<int32_t>(m.right().Value());
+    int64_t value = m.right().Value();
     if (base::bits::IsPowerOfTwo32(value)) {
       Emit(kMips64Dshl | AddressingModeField::encode(kMode_None),
            g.DefineAsRegister(node), g.UseRegister(m.left().node()),
@@ -666,8 +666,8 @@ void InstructionSelector::VisitCall(Node* node, BasicBlock* handler) {
 
   FrameStateDescriptor* frame_state_descriptor = nullptr;
   if (descriptor->NeedsFrameState()) {
-    frame_state_descriptor = GetFrameStateDescriptor(
-        node->InputAt(static_cast<int>(descriptor->InputCount())));
+    frame_state_descriptor =
+        GetFrameStateDescriptor(node->InputAt(descriptor->InputCount()));
   }
 
   CallBuffer buffer(zone(), descriptor, frame_state_descriptor);
@@ -675,12 +675,12 @@ void InstructionSelector::VisitCall(Node* node, BasicBlock* handler) {
   // Compute InstructionOperands for inputs and outputs.
   InitializeCallBuffer(node, &buffer, true, false);
 
-  const int32_t push_count = static_cast<int32_t>(buffer.pushed_nodes.size());
+  int push_count = buffer.pushed_nodes.size();
   if (push_count > 0) {
     Emit(kMips64StackClaim, g.NoOutput(),
          g.TempImmediate(push_count << kPointerSizeLog2));
   }
-  int32_t slot = push_count - 1;
+  int slot = buffer.pushed_nodes.size() - 1;
   for (Node* node : base::Reversed(buffer.pushed_nodes)) {
     Emit(kMips64StoreToStackSlot, g.NoOutput(), g.UseRegister(node),
          g.TempImmediate(slot << kPointerSizeLog2));
@@ -771,12 +771,12 @@ void InstructionSelector::VisitTailCall(Node* node) {
     // Compute InstructionOperands for inputs and outputs.
     InitializeCallBuffer(node, &buffer, true, false);
 
-    const int32_t push_count = static_cast<int32_t>(buffer.pushed_nodes.size());
+    int push_count = buffer.pushed_nodes.size();
     if (push_count > 0) {
       Emit(kMips64StackClaim, g.NoOutput(),
            g.TempImmediate(push_count << kPointerSizeLog2));
     }
-    int slot = push_count - 1;
+    int slot = buffer.pushed_nodes.size() - 1;
     for (Node* node : base::Reversed(buffer.pushed_nodes)) {
       Emit(kMips64StoreToStackSlot, g.NoOutput(), g.UseRegister(node),
            g.TempImmediate(slot << kPointerSizeLog2));

src/ic/mips64/stub-cache-mips64.cc

@@ -57,16 +57,14 @@ static void ProbeTable(Isolate* isolate, MacroAssembler* masm,
   __ Branch(&miss, ne, name, Operand(at));
 
   // Check the map matches.
-  __ ld(at, MemOperand(base_addr,
-                       static_cast<int32_t>(map_off_addr - key_off_addr)));
+  __ ld(at, MemOperand(base_addr, map_off_addr - key_off_addr));
   __ ld(scratch2, FieldMemOperand(receiver, HeapObject::kMapOffset));
   __ Branch(&miss, ne, at, Operand(scratch2));
 
   // Get the code entry from the cache.
   Register code = scratch2;
   scratch2 = no_reg;
-  __ ld(code, MemOperand(base_addr,
-                         static_cast<int32_t>(value_off_addr - key_off_addr)));
+  __ ld(code, MemOperand(base_addr, value_off_addr - key_off_addr));
 
   // Check that the flags match what we're looking for.
   Register flags_reg = base_addr;

src/mips64/assembler-mips64.cc

@@ -211,14 +211,13 @@ Operand::Operand(Handle<Object> handle) {
 }
 
 
-MemOperand::MemOperand(Register rm, int32_t offset) : Operand(rm) {
+MemOperand::MemOperand(Register rm, int64_t offset) : Operand(rm) {
   offset_ = offset;
 }
 
 
-MemOperand::MemOperand(Register rm, int32_t unit, int32_t multiplier,
-                       OffsetAddend offset_addend)
-    : Operand(rm) {
+MemOperand::MemOperand(Register rm, int64_t unit, int64_t multiplier,
+                       OffsetAddend offset_addend) : Operand(rm) {
   offset_ = unit * multiplier + offset_addend;
 }
 
@@ -291,8 +290,7 @@ void Assembler::GetCode(CodeDesc* desc) {
   desc->buffer = buffer_;
   desc->buffer_size = buffer_size_;
   desc->instr_size = pc_offset();
-  desc->reloc_size =
-      static_cast<int>((buffer_ + buffer_size_) - reloc_info_writer.pos());
+  desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
   desc->origin = this;
 }
 
@@ -743,7 +741,7 @@ void Assembler::target_at_put(int pos, int target_pos, bool is_internal) {
     DCHECK((imm28 & 3) == 0);
 
     instr &= ~kImm26Mask;
-    uint32_t imm26 = static_cast<uint32_t>(imm28 >> 2);
+    uint32_t imm26 = imm28 >> 2;
     DCHECK(is_uint26(imm26));
 
     instr_at_put(pos, instr | (imm26 & kImm26Mask));
@@ -1387,7 +1385,7 @@ void Assembler::j(int64_t target) {
     DCHECK(in_range && ((target & 3) == 0));
   }
 #endif
-  GenInstrJump(J, static_cast<uint32_t>(target >> 2) & kImm26Mask);
+  GenInstrJump(J, (target >> 2) & kImm26Mask);
 }
 
 
@@ -1416,7 +1414,7 @@ void Assembler::jal(int64_t target) {
   }
 #endif
   positions_recorder()->WriteRecordedPositions();
-  GenInstrJump(JAL, static_cast<uint32_t>(target >> 2) & kImm26Mask);
+  GenInstrJump(JAL, (target >> 2) & kImm26Mask);
 }
 
 
@@ -2903,8 +2901,7 @@ void Assembler::GrowBuffer() {
   desc.buffer = NewArray<byte>(desc.buffer_size);
 
   desc.instr_size = pc_offset();
-  desc.reloc_size =
-      static_cast<int>((buffer_ + buffer_size_) - reloc_info_writer.pos());
+  desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
 
   // Copy the data.
   intptr_t pc_delta = desc.buffer - buffer_;

src/mips64/assembler-mips64.h

@@ -404,8 +404,8 @@ class MemOperand : public Operand {
     offset_zero = 0
   };
 
-  explicit MemOperand(Register rn, int32_t offset = 0);
-  explicit MemOperand(Register rn, int32_t unit, int32_t multiplier,
+  explicit MemOperand(Register rn, int64_t offset = 0);
+  explicit MemOperand(Register rn, int64_t unit, int64_t multiplier,
                       OffsetAddend offset_addend = offset_zero);
   int32_t offset() const { return offset_; }
 
@@ -1138,9 +1138,7 @@ class Assembler : public AssemblerBase {
   inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; }
 
   // Get the number of bytes available in the buffer.
-  inline intptr_t available_space() const {
-    return reloc_info_writer.pos() - pc_;
-  }
+  inline int available_space() const { return reloc_info_writer.pos() - pc_; }
 
   // Read/patch instructions.
   static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); }

src/mips64/disasm-mips64.cc

@@ -272,7 +272,7 @@ void Decoder::PrintXImm21(Instruction* instr) {
 
 // Print 26-bit immediate value.
 void Decoder::PrintXImm26(Instruction* instr) {
-  uint32_t imm = static_cast<uint32_t>(instr->Imm26Value()) << kImmFieldShift;
+  uint32_t imm = instr->Imm26Value() << kImmFieldShift;
   out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
 }
 

src/mips64/lithium-codegen-mips64.cc

@@ -489,7 +489,7 @@ int32_t LCodeGen::ToInteger32(LConstantOperand* op) const {
 }
 
 
-int64_t LCodeGen::ToRepresentation_donotuse(LConstantOperand* op,
+int32_t LCodeGen::ToRepresentation_donotuse(LConstantOperand* op,
                                    const Representation& r) const {
   HConstant* constant = chunk_->LookupConstant(op);
   int32_t value = constant->Integer32Value();

src/mips64/lithium-codegen-mips64.h

@@ -75,7 +75,7 @@ class LCodeGen: public LCodeGenBase {
   DoubleRegister EmitLoadDoubleRegister(LOperand* op,
                                         FloatRegister flt_scratch,
                                         DoubleRegister dbl_scratch);
-  int64_t ToRepresentation_donotuse(LConstantOperand* op,
+  int32_t ToRepresentation_donotuse(LConstantOperand* op,
                                     const Representation& r) const;
   int32_t ToInteger32(LConstantOperand* op) const;
   Smi* ToSmi(LConstantOperand* op) const;

src/mips64/macro-assembler-mips64.cc

@@ -622,7 +622,7 @@ void MacroAssembler::Addu(Register rd, Register rs, const Operand& rt) {
     addu(rd, rs, rt.rm());
   } else {
     if (is_int16(rt.imm64_) && !MustUseReg(rt.rmode_)) {
-      addiu(rd, rs, static_cast<int32_t>(rt.imm64_));
+      addiu(rd, rs, rt.imm64_);
     } else {
       // li handles the relocation.
       DCHECK(!rs.is(at));
@@ -638,7 +638,7 @@ void MacroAssembler::Daddu(Register rd, Register rs, const Operand& rt) {
     daddu(rd, rs, rt.rm());
   } else {
     if (is_int16(rt.imm64_) && !MustUseReg(rt.rmode_)) {
-      daddiu(rd, rs, static_cast<int32_t>(rt.imm64_));
+      daddiu(rd, rs, rt.imm64_);
     } else {
       // li handles the relocation.
       DCHECK(!rs.is(at));
@@ -654,8 +654,7 @@ void MacroAssembler::Subu(Register rd, Register rs, const Operand& rt) {
     subu(rd, rs, rt.rm());
   } else {
     if (is_int16(rt.imm64_) && !MustUseReg(rt.rmode_)) {
-      addiu(rd, rs, static_cast<int32_t>(
-                        -rt.imm64_));  // No subiu instr, use addiu(x, y, -imm).
+      addiu(rd, rs, -rt.imm64_);  // No subiu instr, use addiu(x, y, -imm).
     } else {
       // li handles the relocation.
       DCHECK(!rs.is(at));
@@ -671,9 +670,7 @@ void MacroAssembler::Dsubu(Register rd, Register rs, const Operand& rt) {
     dsubu(rd, rs, rt.rm());
   } else {
     if (is_int16(rt.imm64_) && !MustUseReg(rt.rmode_)) {
-      daddiu(rd, rs,
-             static_cast<int32_t>(
-                 -rt.imm64_));  // No subiu instr, use addiu(x, y, -imm).
+      daddiu(rd, rs, -rt.imm64_);  // No subiu instr, use addiu(x, y, -imm).
     } else {
       // li handles the relocation.
       DCHECK(!rs.is(at));
@@ -1070,7 +1067,7 @@ void MacroAssembler::And(Register rd, Register rs, const Operand& rt) {
     and_(rd, rs, rt.rm());
   } else {
     if (is_uint16(rt.imm64_) && !MustUseReg(rt.rmode_)) {
-      andi(rd, rs, static_cast<int32_t>(rt.imm64_));
+      andi(rd, rs, rt.imm64_);
     } else {
       // li handles the relocation.
       DCHECK(!rs.is(at));
@@ -1086,7 +1083,7 @@ void MacroAssembler::Or(Register rd, Register rs, const Operand& rt) {
     or_(rd, rs, rt.rm());
   } else {
     if (is_uint16(rt.imm64_) && !MustUseReg(rt.rmode_)) {
-      ori(rd, rs, static_cast<int32_t>(rt.imm64_));
+      ori(rd, rs, rt.imm64_);
     } else {
       // li handles the relocation.
       DCHECK(!rs.is(at));
@@ -1102,7 +1099,7 @@ void MacroAssembler::Xor(Register rd, Register rs, const Operand& rt) {
     xor_(rd, rs, rt.rm());
   } else {
     if (is_uint16(rt.imm64_) && !MustUseReg(rt.rmode_)) {
-      xori(rd, rs, static_cast<int32_t>(rt.imm64_));
+      xori(rd, rs, rt.imm64_);
     } else {
       // li handles the relocation.
       DCHECK(!rs.is(at));
@@ -1139,7 +1136,7 @@ void MacroAssembler::Slt(Register rd, Register rs, const Operand& rt) {
     slt(rd, rs, rt.rm());
   } else {
     if (is_int16(rt.imm64_) && !MustUseReg(rt.rmode_)) {
-      slti(rd, rs, static_cast<int32_t>(rt.imm64_));
+      slti(rd, rs, rt.imm64_);
     } else {
       // li handles the relocation.
       DCHECK(!rs.is(at));
@@ -1155,7 +1152,7 @@ void MacroAssembler::Sltu(Register rd, Register rs, const Operand& rt) {
     sltu(rd, rs, rt.rm());
   } else {
     if (is_int16(rt.imm64_) && !MustUseReg(rt.rmode_)) {
-      sltiu(rd, rs, static_cast<int32_t>(rt.imm64_));
+      sltiu(rd, rs, rt.imm64_);
     } else {
       // li handles the relocation.
       DCHECK(!rs.is(at));
@@ -2334,7 +2331,7 @@ void MacroAssembler::BranchShort(int16_t offset, Condition cond, Register rs,
         if (rt.imm64_ == 0) {
           bgez(rs, offset);
         } else if (is_int16(rt.imm64_)) {
-          slti(scratch, rs, static_cast<int32_t>(rt.imm64_));
+          slti(scratch, rs, rt.imm64_);
           beq(scratch, zero_reg, offset);
         } else {
           r2 = scratch;
@@ -2347,7 +2344,7 @@ void MacroAssembler::BranchShort(int16_t offset, Condition cond, Register rs,
         if (rt.imm64_ == 0) {
           bltz(rs, offset);
         } else if (is_int16(rt.imm64_)) {
-          slti(scratch, rs, static_cast<int32_t>(rt.imm64_));
+          slti(scratch, rs, rt.imm64_);
           bne(scratch, zero_reg, offset);
         } else {
           r2 = scratch;
@@ -2381,7 +2378,7 @@ void MacroAssembler::BranchShort(int16_t offset, Condition cond, Register rs,
         if (rt.imm64_ == 0) {
           b(offset);
         } else if (is_int16(rt.imm64_)) {
-          sltiu(scratch, rs, static_cast<int32_t>(rt.imm64_));
+          sltiu(scratch, rs, rt.imm64_);
           beq(scratch, zero_reg, offset);
         } else {
           r2 = scratch;
@@ -2395,7 +2392,7 @@ void MacroAssembler::BranchShort(int16_t offset, Condition cond, Register rs,
           // No code needs to be emitted.
           return;
         } else if (is_int16(rt.imm64_)) {
-          sltiu(scratch, rs, static_cast<int32_t>(rt.imm64_));
+          sltiu(scratch, rs, rt.imm64_);
           bne(scratch, zero_reg, offset);
         } else {
           r2 = scratch;
@@ -2601,7 +2598,7 @@ void MacroAssembler::BranchShort(Label* L, Condition cond, Register rs,
           offset = shifted_branch_offset(L, false);
           bgez(rs, offset);
         } else if (is_int16(rt.imm64_)) {
-          slti(scratch, rs, static_cast<int32_t>(rt.imm64_));
+          slti(scratch, rs, rt.imm64_);
           offset = shifted_branch_offset(L, false);
           beq(scratch, zero_reg, offset);
         } else {
@@ -2618,7 +2615,7 @@ void MacroAssembler::BranchShort(Label* L, Condition cond, Register rs,
           offset = shifted_branch_offset(L, false);
           bltz(rs, offset);
         } else if (is_int16(rt.imm64_)) {
-          slti(scratch, rs, static_cast<int32_t>(rt.imm64_));
+          slti(scratch, rs, rt.imm64_);
           offset = shifted_branch_offset(L, false);
           bne(scratch, zero_reg, offset);
         } else {
@@ -2662,7 +2659,7 @@ void MacroAssembler::BranchShort(Label* L, Condition cond, Register rs,
           offset = shifted_branch_offset(L, false);
           b(offset);
         } else if (is_int16(rt.imm64_)) {
-          sltiu(scratch, rs, static_cast<int32_t>(rt.imm64_));
+          sltiu(scratch, rs, rt.imm64_);
           offset = shifted_branch_offset(L, false);
           beq(scratch, zero_reg, offset);
         } else {
@@ -2679,7 +2676,7 @@ void MacroAssembler::BranchShort(Label* L, Condition cond, Register rs,
           // No code needs to be emitted.
           return;
         } else if (is_int16(rt.imm64_)) {
-          sltiu(scratch, rs, static_cast<int32_t>(rt.imm64_));
+          sltiu(scratch, rs, rt.imm64_);
           offset = shifted_branch_offset(L, false);
           bne(scratch, zero_reg, offset);
         } else {
@@ -3459,7 +3456,7 @@ void MacroAssembler::Allocate(int object_size,
       Check(eq, kUnexpectedAllocationTop, result, Operand(t9));
     }
     // Load allocation limit into t9. Result already contains allocation top.
-    ld(t9, MemOperand(topaddr, static_cast<int32_t>(limit - top)));
+    ld(t9, MemOperand(topaddr, limit - top));
   }
 
   DCHECK(kPointerSize == kDoubleSize);
@@ -3535,7 +3532,7 @@ void MacroAssembler::Allocate(Register object_size,
       Check(eq, kUnexpectedAllocationTop, result, Operand(t9));
     }
     // Load allocation limit into t9. Result already contains allocation top.
-    ld(t9, MemOperand(topaddr, static_cast<int32_t>(limit - top)));
+    ld(t9, MemOperand(topaddr, limit - top));
   }
 
   DCHECK(kPointerSize == kDoubleSize);
@@ -4463,18 +4460,17 @@ void MacroAssembler::AdduAndCheckForOverflow(Register dst, Register left,
   } else {
     if (dst.is(left)) {
       mov(scratch, left);                    // Preserve left.
-      daddiu(dst, left,
-             static_cast<int32_t>(right.immediate()));  // Left is overwritten.
+      daddiu(dst, left, right.immediate());  // Left is overwritten.
       xor_(scratch, dst, scratch);           // Original left.
       // Load right since xori takes uint16 as immediate.
-      daddiu(t9, zero_reg, static_cast<int32_t>(right.immediate()));
+      daddiu(t9, zero_reg, right.immediate());
       xor_(overflow_dst, dst, t9);
       and_(overflow_dst, overflow_dst, scratch);
     } else {
-      daddiu(dst, left, static_cast<int32_t>(right.immediate()));
+      daddiu(dst, left, right.immediate());
       xor_(overflow_dst, dst, left);
       // Load right since xori takes uint16 as immediate.
-      daddiu(t9, zero_reg, static_cast<int32_t>(right.immediate()));
+      daddiu(t9, zero_reg, right.immediate());
       xor_(scratch, dst, t9);
       and_(overflow_dst, scratch, overflow_dst);
     }
@@ -4533,18 +4529,17 @@ void MacroAssembler::SubuAndCheckForOverflow(Register dst, Register left,
   } else {
     if (dst.is(left)) {
       mov(scratch, left);                       // Preserve left.
-      daddiu(dst, left,
-             static_cast<int32_t>(-right.immediate()));  // Left is overwritten.
+      daddiu(dst, left, -(right.immediate()));  // Left is overwritten.
       xor_(overflow_dst, dst, scratch);         // scratch is original left.
       // Load right since xori takes uint16 as immediate.
-      daddiu(t9, zero_reg, static_cast<int32_t>(right.immediate()));
+      daddiu(t9, zero_reg, right.immediate());
       xor_(scratch, scratch, t9);  // scratch is original left.
       and_(overflow_dst, scratch, overflow_dst);
     } else {
-      daddiu(dst, left, static_cast<int32_t>(-right.immediate()));
+      daddiu(dst, left, -(right.immediate()));
       xor_(overflow_dst, dst, left);
       // Load right since xori takes uint16 as immediate.
-      daddiu(t9, zero_reg, static_cast<int32_t>(right.immediate()));
+      daddiu(t9, zero_reg, right.immediate());
       xor_(scratch, left, t9);
       and_(overflow_dst, scratch, overflow_dst);
     }
@@ -4845,7 +4840,8 @@ void MacroAssembler::LoadTransitionedArrayMapConditional(
   ld(scratch,
      MemOperand(scratch,
                 Context::SlotOffset(Context::JS_ARRAY_MAPS_INDEX)));
-  int offset = expected_kind * kPointerSize + FixedArrayBase::kHeaderSize;
+  size_t offset = expected_kind * kPointerSize +
+      FixedArrayBase::kHeaderSize;
   ld(at, FieldMemOperand(scratch, offset));
   Branch(no_map_match, ne, map_in_out, Operand(at));
 

src/mips64/simulator-mips64.cc

@@ -782,7 +782,7 @@ static uint32_t ICacheHash(void* key) {
 }
 
 
-static bool AllOnOnePage(uintptr_t start, size_t size) {
+static bool AllOnOnePage(uintptr_t start, int size) {
   intptr_t start_page = (start & ~CachePage::kPageMask);
   intptr_t end_page = ((start + size) & ~CachePage::kPageMask);
   return start_page == end_page;
@@ -830,8 +830,9 @@ CachePage* Simulator::GetCachePage(v8::internal::HashMap* i_cache, void* page) {
 
 
 // Flush from start up to and not including start + size.
-void Simulator::FlushOnePage(v8::internal::HashMap* i_cache, intptr_t start,
-                             size_t size) {
+void Simulator::FlushOnePage(v8::internal::HashMap* i_cache,
+                             intptr_t start,
+                             int size) {
   DCHECK(size <= CachePage::kPageSize);
   DCHECK(AllOnOnePage(start, size - 1));
   DCHECK((start & CachePage::kLineMask) == 0);
@@ -1154,7 +1155,7 @@ void Simulator::GetFpArgs(double* x, double* y, int32_t* z) {
     const int fparg2 = (kMipsAbi == kN64) ? 13 : 14;
     *x = get_fpu_register_double(12);
     *y = get_fpu_register_double(fparg2);
-    *z = static_cast<int32_t>(get_register(a2));
+    *z = get_register(a2);
   } else {
   // TODO(plind): bad ABI stuff, refactor or remove.
     // We use a char buffer to get around the strict-aliasing rules which
@@ -1630,7 +1631,7 @@ uint32_t Simulator::ReadWU(int64_t addr, Instruction* instr) {
 }
 
 
-void Simulator::WriteW(int64_t addr, int32_t value, Instruction* instr) {
+void Simulator::WriteW(int64_t addr, int value, Instruction* instr) {
   if (addr >= 0 && addr < 0x400) {
     // This has to be a NULL-dereference, drop into debugger.
     PrintF("Memory write to bad address: 0x%08lx, pc=0x%08lx\n",
@@ -2182,10 +2183,14 @@ void Simulator::SignalExceptions() {
 
 // Handle execution based on instruction types.
 
-void Simulator::ConfigureTypeRegister(Instruction* instr, int64_t* alu_out,
-                                      int64_t* i64hilo, uint64_t* u64hilo,
-                                      int64_t* next_pc, int* return_addr_reg,
-                                      bool* do_interrupt, int64_t* i128resultH,
+void Simulator::ConfigureTypeRegister(Instruction* instr,
+                                      int64_t* alu_out,
+                                      int64_t* i64hilo,
+                                      uint64_t* u64hilo,
+                                      int64_t* next_pc,
+                                      int64_t* return_addr_reg,
+                                      bool* do_interrupt,
+                                      int64_t* i128resultH,
                                       int64_t* i128resultL) {
   // Every local variable declared here needs to be const.
   // This is to make sure that changed values are sent back to
@@ -2193,13 +2198,13 @@ void Simulator::ConfigureTypeRegister(Instruction* instr, int64_t* alu_out,
 
   // Instruction fields.
   const Opcode   op     = instr->OpcodeFieldRaw();
-  const int32_t  rs_reg = instr->RsValue();
+  const int64_t  rs_reg = instr->RsValue();
   const int64_t  rs     = get_register(rs_reg);
   const uint64_t rs_u   = static_cast<uint64_t>(rs);
-  const int32_t  rt_reg = instr->RtValue();
+  const int64_t  rt_reg = instr->RtValue();
   const int64_t  rt     = get_register(rt_reg);
   const uint64_t rt_u   = static_cast<uint64_t>(rt);
-  const int32_t  rd_reg = instr->RdValue();
+  const int64_t  rd_reg = instr->RdValue();
   const uint64_t sa     = instr->SaValue();
 
   const int32_t  fs_reg = instr->FsValue();
@@ -2268,8 +2273,7 @@ void Simulator::ConfigureTypeRegister(Instruction* instr, int64_t* alu_out,
             // is special case of SRL instruction, added in MIPS32 Release 2.
             // RS field is equal to 00001.
             *alu_out = static_cast<int32_t>(
-                base::bits::RotateRight32(static_cast<const uint32_t>(rt_u),
-                                          static_cast<const uint32_t>(sa)));
+                base::bits::RotateRight32((uint32_t)rt_u, sa));
           }
           break;
         case DSRL:
@@ -2303,8 +2307,7 @@ void Simulator::ConfigureTypeRegister(Instruction* instr, int64_t* alu_out,
             // This is special case od SRLV instruction, added in MIPS32
             // Release 2. SA field is equal to 00001.
             *alu_out = static_cast<int32_t>(
-                base::bits::RotateRight32(static_cast<const uint32_t>(rt_u),
-                                          static_cast<const uint32_t>(rs_u)));
+                base::bits::RotateRight32((uint32_t)rt_u, rs_u));
           }
           break;
         case DSRLV:
@@ -2316,9 +2319,7 @@ void Simulator::ConfigureTypeRegister(Instruction* instr, int64_t* alu_out,
             // Logical right-rotate of a word by a variable number of bits.
             // This is special case od SRLV instruction, added in MIPS32
             // Release 2. SA field is equal to 00001.
-            *alu_out =
-                base::bits::RotateRight32(static_cast<const uint32_t>(rt_u),
-                                          static_cast<const uint32_t>(rs_u));
+            *alu_out = base::bits::RotateRight32(rt_u, rs_u);
           }
           break;
         case SRAV:
@@ -2384,11 +2385,11 @@ void Simulator::ConfigureTypeRegister(Instruction* instr, int64_t* alu_out,
           *alu_out = rs + rt;
           break;
         case ADDU: {
-          int32_t alu32_out = static_cast<int32_t>(rs + rt);
+            int32_t alu32_out = rs + rt;
             // Sign-extend result of 32bit operation into 64bit register.
             *alu_out = static_cast<int64_t>(alu32_out);
-          break;
           }
+          break;
         case DADDU:
           *alu_out = rs + rt;
           break;
@@ -2404,11 +2405,11 @@ void Simulator::ConfigureTypeRegister(Instruction* instr, int64_t* alu_out,
           *alu_out = rs - rt;
           break;
         case SUBU: {
-          int32_t alu32_out = static_cast<int32_t>(rs - rt);
+            int32_t alu32_out = rs - rt;
             // Sign-extend result of 32bit operation into 64bit register.
             *alu_out = static_cast<int64_t>(alu32_out);
-          break;
           }
+          break;
         case DSUBU:
           *alu_out = rs - rt;
           break;
@@ -2480,8 +2481,7 @@ void Simulator::ConfigureTypeRegister(Instruction* instr, int64_t* alu_out,
         case CLZ:
           // MIPS32 spec: If no bits were set in GPR rs, the result written to
           // GPR rd is 32.
-          *alu_out =
-              base::bits::CountLeadingZeros32(static_cast<uint32_t>(rs_u));
+          *alu_out = base::bits::CountLeadingZeros32(rs_u);
           break;
         default:
           UNREACHABLE();
@@ -2586,9 +2586,9 @@ void Simulator::ConfigureTypeRegister(Instruction* instr, int64_t* alu_out,
 
 
 void Simulator::DecodeTypeRegisterSRsType(Instruction* instr,
-                                          const int32_t fs_reg,
-                                          const int32_t ft_reg,
-                                          const int32_t fd_reg) {
+                                          const int32_t& fs_reg,
+                                          const int32_t& ft_reg,
+                                          const int32_t& fd_reg) {
   float fs, ft, fd;
   fs = get_fpu_register_float(fs_reg);
   ft = get_fpu_register_float(ft_reg);
@@ -2988,9 +2988,9 @@ void Simulator::DecodeTypeRegisterSRsType(Instruction* instr,
 
 
 void Simulator::DecodeTypeRegisterDRsType(Instruction* instr,
-                                          const int32_t fs_reg,
-                                          const int32_t ft_reg,
-                                          const int32_t fd_reg) {
+                                          const int32_t& fs_reg,
+                                          const int32_t& ft_reg,
+                                          const int32_t& fd_reg) {
   double ft, fs, fd;
   uint32_t cc, fcsr_cc;
   fs = get_fpu_register_double(fs_reg);
@@ -3387,9 +3387,9 @@ void Simulator::DecodeTypeRegisterDRsType(Instruction* instr,
 
 
 void Simulator::DecodeTypeRegisterWRsType(Instruction* instr,
-                                          const int32_t fs_reg,
-                                          const int32_t fd_reg,
-                                          const int32_t ft_reg,
+                                          const int32_t& fs_reg,
+                                          const int32_t& fd_reg,
+                                          const int32_t& ft_reg,
                                           int64_t& alu_out) {
   float fs = get_fpu_register_float(fs_reg);
   float ft = get_fpu_register_float(ft_reg);
@@ -3482,9 +3482,9 @@ void Simulator::DecodeTypeRegisterWRsType(Instruction* instr,
 
 
 void Simulator::DecodeTypeRegisterLRsType(Instruction* instr,
-                                          const int32_t fs_reg,
-                                          const int32_t fd_reg,
-                                          const int32_t ft_reg) {
+                                          const int32_t& fs_reg,
+                                          const int32_t& fd_reg,
+                                          const int32_t& ft_reg) {
   double fs = get_fpu_register_double(fs_reg);
   double ft = get_fpu_register_double(ft_reg);
   int64_t i64;
@@ -3575,11 +3575,12 @@ void Simulator::DecodeTypeRegisterLRsType(Instruction* instr,
   }
 }
 
+
 void Simulator::DecodeTypeRegisterCOP1(
-    Instruction* instr, const int32_t rs_reg, const int64_t rs,
-    const uint64_t rs_u, const int32_t rt_reg, const int64_t rt,
-    const uint64_t rt_u, const int32_t rd_reg, const int32_t fr_reg,
-    const int32_t fs_reg, const int32_t ft_reg, const int32_t fd_reg,
+    Instruction* instr, const int32_t& rs_reg, const int64_t& rs,
+    const uint64_t& rs_u, const int32_t& rt_reg, const int64_t& rt,
+    const uint64_t& rt_u, const int32_t& rd_reg, const int32_t& fr_reg,
+    const int32_t& fs_reg, const int32_t& ft_reg, const int32_t& fd_reg,
     int64_t& alu_out) {
   switch (instr->RsFieldRaw()) {
     case BC1:  // Branch on coprocessor condition.
@@ -3598,19 +3599,18 @@ void Simulator::DecodeTypeRegisterCOP1(
     case CTC1:
       // At the moment only FCSR is supported.
       DCHECK(fs_reg == kFCSRRegister);
-      FCSR_ = static_cast<uint32_t>(registers_[rt_reg]);
+      FCSR_ = registers_[rt_reg];
       break;
     case MTC1:
       // Hardware writes upper 32-bits to zero on mtc1.
       set_fpu_register_hi_word(fs_reg, 0);
-      set_fpu_register_word(fs_reg, static_cast<int32_t>(registers_[rt_reg]));
+      set_fpu_register_word(fs_reg, registers_[rt_reg]);
       break;
     case DMTC1:
       set_fpu_register(fs_reg, registers_[rt_reg]);
       break;
     case MTHC1:
-      set_fpu_register_hi_word(fs_reg,
-                               static_cast<int32_t>(registers_[rt_reg]));
+      set_fpu_register_hi_word(fs_reg, registers_[rt_reg]);
       break;
     case S:
       DecodeTypeRegisterSRsType(instr, fs_reg, ft_reg, fd_reg);
@@ -3631,10 +3631,10 @@ void Simulator::DecodeTypeRegisterCOP1(
 
 
 void Simulator::DecodeTypeRegisterCOP1X(Instruction* instr,
-                                        const int32_t fr_reg,
-                                        const int32_t fs_reg,
-                                        const int32_t ft_reg,
-                                        const int32_t fd_reg) {
+                                        const int32_t& fr_reg,
+                                        const int32_t& fs_reg,
+                                        const int32_t& ft_reg,
+                                        const int32_t& fd_reg) {
   switch (instr->FunctionFieldRaw()) {
     case MADD_D:
       double fr, ft, fs;
@@ -3650,14 +3650,13 @@ void Simulator::DecodeTypeRegisterCOP1X(Instruction* instr,
 
 
 void Simulator::DecodeTypeRegisterSPECIAL(
-    Instruction* instr, const int32_t rs_reg, const int64_t rs,
-    const uint64_t rs_u, const int32_t rt_reg, const int64_t rt,
-    const uint64_t rt_u, const int32_t rd_reg, const int32_t fr_reg,
-    const int32_t fs_reg, const int32_t ft_reg, const int32_t fd_reg,
-    const int64_t i64hilo, const uint64_t u64hilo, const int64_t alu_out,
-    const bool do_interrupt, const int64_t current_pc, const int64_t next_pc,
-    const int32_t return_addr_reg, const int64_t i128resultH,
-    const int64_t i128resultL) {
+    Instruction* instr, const int64_t& rs_reg, const int64_t& rs,
+    const uint64_t& rs_u, const int64_t& rt_reg, const int64_t& rt,
+    const uint64_t& rt_u, const int64_t& rd_reg, const int32_t& fr_reg,
+    const int32_t& fs_reg, const int32_t& ft_reg, const int64_t& fd_reg,
+    int64_t& i64hilo, uint64_t& u64hilo, int64_t& alu_out, bool& do_interrupt,
+    int64_t& current_pc, int64_t& next_pc, int64_t& return_addr_reg,
+    int64_t& i128resultH, int64_t& i128resultL) {
   switch (instr->FunctionFieldRaw()) {
     case SELEQZ_S:
       DCHECK(kArchVariant == kMips64r6);
@@ -3821,8 +3820,8 @@ void Simulator::DecodeTypeRegisterSPECIAL(
 
 
 void Simulator::DecodeTypeRegisterSPECIAL2(Instruction* instr,
-                                           const int32_t rd_reg,
-                                           int64_t alu_out) {
+                                           const int64_t& rd_reg,
+                                           int64_t& alu_out) {
   switch (instr->FunctionFieldRaw()) {
     case MUL:
       set_register(rd_reg, alu_out);
@@ -3838,9 +3837,9 @@ void Simulator::DecodeTypeRegisterSPECIAL2(Instruction* instr,
 
 
 void Simulator::DecodeTypeRegisterSPECIAL3(Instruction* instr,
-                                           const int32_t rt_reg,
-                                           const int32_t rd_reg,
-                                           const int64_t alu_out) {
+                                           const int64_t& rt_reg,
+                                           const int64_t& rd_reg,
+                                           int64_t& alu_out) {
   switch (instr->FunctionFieldRaw()) {
     case INS:
       // Ins instr leaves result in Rt, rather than Rd.
@@ -3867,13 +3866,13 @@ void Simulator::DecodeTypeRegisterSPECIAL3(Instruction* instr,
 void Simulator::DecodeTypeRegister(Instruction* instr) {
   // Instruction fields.
   const Opcode   op     = instr->OpcodeFieldRaw();
-  const int32_t  rs_reg = instr->RsValue();
+  const int64_t  rs_reg = instr->RsValue();
   const int64_t  rs     = get_register(rs_reg);
   const uint64_t rs_u   = static_cast<uint32_t>(rs);
-  const int32_t  rt_reg = instr->RtValue();
+  const int64_t  rt_reg = instr->RtValue();
   const int64_t  rt     = get_register(rt_reg);
   const uint64_t rt_u   = static_cast<uint32_t>(rt);
-  const int32_t  rd_reg = instr->RdValue();
+  const int64_t  rd_reg = instr->RdValue();
 
   const int32_t fr_reg = instr->FrValue();
   const int32_t fs_reg = instr->FsValue();
@@ -3895,7 +3894,7 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
   int64_t current_pc = get_pc();
   // Next pc
   int64_t next_pc = 0;
-  int32_t return_addr_reg = 31;
+  int64_t return_addr_reg = 31;
 
   int64_t i128resultH;
   int64_t i128resultL;
@@ -3951,7 +3950,7 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
   Opcode   op     = instr->OpcodeFieldRaw();
   int64_t  rs     = get_register(instr->RsValue());
   uint64_t rs_u   = static_cast<uint64_t>(rs);
-  int32_t  rt_reg = instr->RtValue();  // Destination register.
+  int64_t  rt_reg = instr->RtValue();  // Destination register.
   int64_t  rt     = get_register(rt_reg);
   int16_t  imm16  = instr->Imm16Value();
 
@@ -4094,11 +4093,11 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
       alu_out = rs + se_imm16;
       break;
     case ADDIU: {
-      int32_t alu32_out = static_cast<int32_t>(rs + se_imm16);
+        int32_t alu32_out = rs + se_imm16;
         // Sign-extend result of 32bit operation into 64bit register.
         alu_out = static_cast<int64_t>(alu32_out);
-      break;
       }
+      break;
     case DADDIU:
       alu_out = rs + se_imm16;
       break;
@@ -4118,11 +4117,11 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
         alu_out = rs ^ oe_imm16;
       break;
     case LUI: {
-      int32_t alu32_out = static_cast<int32_t>(oe_imm16 << 16);
+        int32_t alu32_out = (oe_imm16 << 16);
         // Sign-extend result of 32bit operation into 64bit register.
         alu_out = static_cast<int64_t>(alu32_out);
-      break;
       }
+      break;
     // ------------- Memory instructions.
     case LB:
       addr = rs + se_imm16;
@@ -4272,16 +4271,16 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
       WriteH(addr, static_cast<uint16_t>(rt), instr);
       break;
     case SWL:
-      WriteW(addr, static_cast<int32_t>(mem_value), instr);
+      WriteW(addr, mem_value, instr);
       break;
     case SW:
-      WriteW(addr, static_cast<int32_t>(rt), instr);
+      WriteW(addr, rt, instr);
       break;
     case SD:
       Write2W(addr, rt, instr);
       break;
     case SWR:
-      WriteW(addr, static_cast<int32_t>(mem_value), instr);
+      WriteW(addr, mem_value, instr);
       break;
     case LWC1:
       set_fpu_register(ft_reg, kFPUInvalidResult);  // Trash upper 32 bits.
@@ -4292,7 +4291,7 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
       break;
     case SWC1:
       addr = rs + se_imm16;
-      WriteW(addr, static_cast<int32_t>(get_fpu_register(ft_reg)), instr);
+      WriteW(addr, get_fpu_register(ft_reg), instr);
       break;
     case SDC1:
       addr = rs + se_imm16;

src/mips64/simulator-mips64.h

@@ -326,55 +326,57 @@ class Simulator {
   inline int32_t SetDoubleLOW(double* addr);
 
   // functions called from DecodeTypeRegister
-  void DecodeTypeRegisterCOP1(Instruction* instr, const int32_t rs_reg,
-                              const int64_t rs, const uint64_t rs_u,
-                              const int32_t rt_reg, const int64_t rt,
-                              const uint64_t rt_u, const int32_t rd_reg,
-                              const int32_t fr_reg, const int32_t fs_reg,
-                              const int32_t ft_reg, const int32_t fd_reg,
+  void DecodeTypeRegisterCOP1(Instruction* instr, const int32_t& rs_reg,
+                              const int64_t& rs, const uint64_t& rs_u,
+                              const int32_t& rt_reg, const int64_t& rt,
+                              const uint64_t& rt_u, const int32_t& rd_reg,
+                              const int32_t& fr_reg, const int32_t& fs_reg,
+                              const int32_t& ft_reg, const int32_t& fd_reg,
                               int64_t& alu_out);
 
-  void DecodeTypeRegisterCOP1X(Instruction* instr, const int32_t fr_reg,
-                               const int32_t fs_reg, const int32_t ft_reg,
-                               const int32_t fd_reg);
+  void DecodeTypeRegisterCOP1X(Instruction* instr, const int32_t& fr_reg,
+                               const int32_t& fs_reg, const int32_t& ft_reg,
+                               const int32_t& fd_reg);
 
   void DecodeTypeRegisterSPECIAL(
-      Instruction* instr, const int32_t rs_reg, const int64_t rs,
-      const uint64_t rs_u, const int32_t rt_reg, const int64_t rt,
-      const uint64_t rt_u, const int32_t rd_reg, const int32_t fr_reg,
-      const int32_t fs_reg, const int32_t ft_reg, const int32_t fd_reg,
-      const int64_t i64hilo, const uint64_t u64hilo, const int64_t alu_out,
-      const bool do_interrupt, const int64_t current_pc, const int64_t next_pc,
-      const int32_t return_addr_reg, const int64_t i128resultH,
-      const int64_t i128resultL);
-
-
-  void DecodeTypeRegisterSPECIAL2(Instruction* instr, const int32_t rd_reg,
-                                  const int64_t alu_out);
+      Instruction* instr, const int64_t& rs_reg, const int64_t& rs,
+      const uint64_t& rs_u, const int64_t& rt_reg, const int64_t& rt,
+      const uint64_t& rt_u, const int64_t& rd_reg, const int32_t& fr_reg,
+      const int32_t& fs_reg, const int32_t& ft_reg, const int64_t& fd_reg,
+      int64_t& i64hilo, uint64_t& u64hilo, int64_t& alu_out, bool& do_interrupt,
+      int64_t& current_pc, int64_t& next_pc, int64_t& return_addr_reg,
+      int64_t& i128resultH, int64_t& i128resultL);
+
+  void DecodeTypeRegisterSPECIAL2(Instruction* instr, const int64_t& rd_reg,
+                                  int64_t& alu_out);
 
-  void DecodeTypeRegisterSPECIAL3(Instruction* instr, const int32_t rt_reg,
-                                  const int32_t rd_reg, const int64_t alu_out);
+  void DecodeTypeRegisterSPECIAL3(Instruction* instr, const int64_t& rt_reg,
+                                  const int64_t& rd_reg, int64_t& alu_out);
 
-  void DecodeTypeRegisterSRsType(Instruction* instr, const int32_t fs_reg,
-                                 const int32_t ft_reg, const int32_t fd_reg);
+  void DecodeTypeRegisterSRsType(Instruction* instr, const int32_t& fs_reg,
+                                 const int32_t& ft_reg, const int32_t& fd_reg);
 
-  void DecodeTypeRegisterDRsType(Instruction* instr, const int32_t fs_reg,
-                                 const int32_t ft_reg, const int32_t fd_reg);
+  void DecodeTypeRegisterDRsType(Instruction* instr, const int32_t& fs_reg,
+                                 const int32_t& ft_reg, const int32_t& fd_reg);
 
-  void DecodeTypeRegisterWRsType(Instruction* instr, const int32_t fs_reg,
-                                 const int32_t ft_reg, const int32_t fd_reg,
+  void DecodeTypeRegisterWRsType(Instruction* instr, const int32_t& fs_reg,
+                                 const int32_t& ft_reg, const int32_t& fd_reg,
                                  int64_t& alu_out);
 
-  void DecodeTypeRegisterLRsType(Instruction* instr, const int32_t fs_reg,
-                                 const int32_t fd_reg, const int32_t ft_reg);
+  void DecodeTypeRegisterLRsType(Instruction* instr, const int32_t& fs_reg,
+                                 const int32_t& fd_reg, const int32_t& ft_reg);
   // Executing is handled based on the instruction type.
   void DecodeTypeRegister(Instruction* instr);
 
   // Helper function for DecodeTypeRegister.
-  void ConfigureTypeRegister(Instruction* instr, int64_t* alu_out,
-                             int64_t* i64hilo, uint64_t* u64hilo,
-                             int64_t* next_pc, int* return_addr_reg,
-                             bool* do_interrupt, int64_t* result128H,
+  void ConfigureTypeRegister(Instruction* instr,
+                             int64_t* alu_out,
+                             int64_t* i64hilo,
+                             uint64_t* u64hilo,
+                             int64_t* next_pc,
+                             int64_t* return_addr_reg,
+                             bool* do_interrupt,
+                             int64_t* result128H,
                              int64_t* result128L);
 
   void DecodeTypeImmediate(Instruction* instr);
@@ -416,7 +418,7 @@ class Simulator {
   // ICache.
   static void CheckICache(v8::internal::HashMap* i_cache, Instruction* instr);
   static void FlushOnePage(v8::internal::HashMap* i_cache, intptr_t start,
-                           size_t size);
+                           int size);
   static CachePage* GetCachePage(v8::internal::HashMap* i_cache, void* page);
 
   enum Exception {
@@ -496,14 +498,12 @@ class Simulator {
 
 #ifdef MIPS_ABI_N64
 #define CALL_GENERATED_REGEXP_CODE(entry, p0, p1, p2, p3, p4, p5, p6, p7, p8) \
-  static_cast<int>(                                                           \
-      Simulator::current(Isolate::Current())                                  \
-          ->Call(entry, 10, p0, p1, p2, p3, p4, p5, p6, p7, NULL, p8))
+    Simulator::current(Isolate::Current())->Call( \
+        entry, 10, p0, p1, p2, p3, p4, p5, p6, p7, NULL, p8)
 #else  // Must be O32 Abi.
 #define CALL_GENERATED_REGEXP_CODE(entry, p0, p1, p2, p3, p4, p5, p6, p7, p8) \
-  static_cast<int>(                                                           \
-      Simulator::current(Isolate::Current())                                  \
-          ->Call(entry, 10, p0, p1, p2, p3, NULL, p4, p5, p6, p7, p8))
+    Simulator::current(Isolate::Current())->Call( \
+        entry, 10, p0, p1, p2, p3, NULL, p4, p5, p6, p7, p8)
 #endif  // MIPS_ABI_N64
 
 

test/cctest/test-assembler-mips64.cc

@@ -3121,9 +3121,8 @@ TEST(jump_tables1) {
 #endif
   F1 f = FUNCTION_CAST<F1>(code->entry());
   for (int i = 0; i < kNumCases; ++i) {
-    int64_t res = reinterpret_cast<int64_t>(
-        CALL_GENERATED_CODE(f, i, 0, 0, 0, 0));
-    ::printf("f(%d) = %" PRId64 "\n", i, res);
+    int res = reinterpret_cast<int64_t>(CALL_GENERATED_CODE(f, i, 0, 0, 0, 0));
+    ::printf("f(%d) = %d\n", i, res);
     CHECK_EQ(values[i], static_cast<int>(res));
   }
 }
@@ -3193,9 +3192,8 @@ TEST(jump_tables2) {
 #endif
   F1 f = FUNCTION_CAST<F1>(code->entry());
   for (int i = 0; i < kNumCases; ++i) {
-    int64_t res = reinterpret_cast<int64_t>(
-        CALL_GENERATED_CODE(f, i, 0, 0, 0, 0));
-    ::printf("f(%d) = %" PRId64 "\n", i, res);
+    int res = reinterpret_cast<int64_t>(CALL_GENERATED_CODE(f, i, 0, 0, 0, 0));
+    ::printf("f(%d) = %d\n", i, res);
     CHECK_EQ(values[i], res);
   }
 }

test/cctest/test-code-stubs-mips64.cc

@@ -144,8 +144,7 @@ int32_t RunGeneratedCodeCallWrapper(ConvertDToIFunc func,
                                     double from) {
 #ifdef USE_SIMULATOR
   Simulator::current(Isolate::Current())->CallFP(FUNCTION_ADDR(func), from, 0.);
-  return static_cast<int32_t>(
-      Simulator::current(Isolate::Current())->get_register(v0.code()));
+  return Simulator::current(Isolate::Current())->get_register(v0.code());
 #else
   return (*func)(from);
 #endif