[wasm-simd][arm64] Prototype i32x4.widen_i8x16_{s,u}

This prototypes i32x4.widen_i8x16_s and i32x4.widen_i8x16_u for arm64.

Bug: v8:11297
Change-Id: Ib9be5086c8ea98340c9bb1980c319626d7072c1e
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2664994Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#72537}

src/compiler/backend/arm64/code-generator-arm64.cc

@@ -2402,6 +2402,66 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ Addp(i.OutputSimd128Register().V4S(), tmp1, tmp2);
       break;
     }
+    case kArm64I32x4WidenI8x16S: {
+      VRegister dst = i.OutputSimd128Register();
+      VRegister src = i.InputSimd128Register(0);
+      uint8_t laneidx = MiscField::decode(instr->opcode());
+      switch (laneidx) {
+        case 0: {
+          __ Sxtl(dst.V8H(), src.V8B());
+          __ Sxtl(dst.V4S(), dst.V4H());
+          break;
+        }
+        case 1: {
+          __ Sxtl(dst.V8H(), src.V8B());
+          __ Sxtl2(dst.V4S(), dst.V8H());
+          break;
+        }
+        case 2: {
+          __ Sxtl2(dst.V8H(), src.V16B());
+          __ Sxtl(dst.V4S(), dst.V4H());
+          break;
+        }
+        case 3: {
+          __ Sxtl2(dst.V8H(), src.V16B());
+          __ Sxtl2(dst.V4S(), dst.V8H());
+          break;
+        }
+        default:
+          UNREACHABLE();
+      }
+      break;
+    }
+    case kArm64I32x4WidenI8x16U: {
+      VRegister dst = i.OutputSimd128Register();
+      VRegister src = i.InputSimd128Register(0);
+      uint8_t laneidx = MiscField::decode(instr->opcode());
+      switch (laneidx) {
+        case 0: {
+          __ Uxtl(dst.V8H(), src.V8B());
+          __ Uxtl(dst.V4S(), dst.V4H());
+          break;
+        }
+        case 1: {
+          __ Uxtl(dst.V8H(), src.V8B());
+          __ Uxtl2(dst.V4S(), dst.V8H());
+          break;
+        }
+        case 2: {
+          __ Uxtl2(dst.V8H(), src.V16B());
+          __ Uxtl(dst.V4S(), dst.V4H());
+          break;
+        }
+        case 3: {
+          __ Uxtl2(dst.V8H(), src.V16B());
+          __ Uxtl2(dst.V4S(), dst.V8H());
+          break;
+        }
+        default:
+          UNREACHABLE();
+      }
+      break;
+    }
     case kArm64I16x8Splat: {
       __ Dup(i.OutputSimd128Register().V8H(), i.InputRegister32(0));
       break;

src/compiler/backend/arm64/instruction-codes-arm64.h

@@ -270,6 +270,8 @@ namespace compiler {
   V(Arm64I32x4DotI16x8S)                    \
   V(Arm64I32x4TruncSatF64x2SZero)           \
   V(Arm64I32x4TruncSatF64x2UZero)           \
+  V(Arm64I32x4WidenI8x16S)                  \
+  V(Arm64I32x4WidenI8x16U)                  \
   V(Arm64I16x8Splat)                        \
   V(Arm64I16x8ExtractLaneU)                 \
   V(Arm64I16x8ExtractLaneS)                 \

src/compiler/backend/arm64/instruction-scheduler-arm64.cc

@@ -239,6 +239,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArm64I32x4DotI16x8S:
     case kArm64I32x4TruncSatF64x2SZero:
     case kArm64I32x4TruncSatF64x2UZero:
+    case kArm64I32x4WidenI8x16S:
+    case kArm64I32x4WidenI8x16U:
     case kArm64I16x8Splat:
     case kArm64I16x8ExtractLaneU:
     case kArm64I16x8ExtractLaneS:

src/compiler/backend/arm64/instruction-selector-arm64.cc

@@ -3963,6 +3963,24 @@ void InstructionSelector::VisitI8x16Popcnt(Node* node) {
   VisitRR(this, code, node);
 }
 
+void InstructionSelector::VisitI32x4WidenI8x16S(Node* node) {
+  InstructionCode opcode = kArm64I32x4WidenI8x16S;
+  uint8_t laneidx = OpParameter<uint8_t>(node->op());
+  DCHECK_GT(4, laneidx);
+  opcode |= LaneSizeField::encode(laneidx);
+  Arm64OperandGenerator g(this);
+  Emit(opcode, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
+}
+
+void InstructionSelector::VisitI32x4WidenI8x16U(Node* node) {
+  InstructionCode opcode = kArm64I32x4WidenI8x16U;
+  uint8_t laneidx = OpParameter<uint8_t>(node->op());
+  DCHECK_GT(4, laneidx);
+  opcode |= LaneSizeField::encode(laneidx);
+  Arm64OperandGenerator g(this);
+  Emit(opcode, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
+}
+
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {

src/compiler/backend/instruction-selector.cc

@@ -2808,12 +2808,12 @@ void InstructionSelector::VisitI32x4TruncSatF64x2UZero(Node* node) {
 }
 #endif  //! V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_IA32
 
-#if !V8_TARGET_ARCH_X64
+#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64
 // TODO(v8:11297) Prototype i32x4.widen_i8x16_u
 void InstructionSelector::VisitI32x4WidenI8x16S(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI32x4WidenI8x16U(Node* node) { UNIMPLEMENTED(); }
-#endif  // !V8_TARGET_ARCH_X64
+#endif  // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64
 
 #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_IA32
 void InstructionSelector::VisitI64x2Ne(Node* node) { UNIMPLEMENTED(); }

test/cctest/wasm/test-run-wasm-simd.cc

@@ -2213,7 +2213,7 @@ WASM_SIMD_TEST(I32x4ShrU) {
                       LogicalShiftRight);
 }
 
-#if V8_TARGET_ARCH_X64
+#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 // TODO(v8:11297) Prototype i32x4.widen_i8x16_{u,s}
 WASM_SIMD_TEST_NO_LOWERING(I32x4WidenI8x16U) {
   FLAG_SCOPE(wasm_simd_post_mvp);
@@ -2287,7 +2287,7 @@ WASM_SIMD_TEST_NO_LOWERING(I32x4WidenI8x16S) {
     }
   }
 }
-#endif  // V8_TARGET_ARCH_X64
+#endif  // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 
 // Tests both signed and unsigned conversion from I8x16 (unpacking).
 WASM_SIMD_TEST(I16x8ConvertI8x16) {