[relaxed-simd] Move qfma and approx behind relaxed-simd flag

Move them from post-mvp to relaxed-simd flag.

We will have a follow up change to move all the relaxed-simd tests into
their own file.

Bug: v8:11583
Change-Id: Iea9809a309bac428c856e5d0bd024fe0070d5921
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2773898Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#73524}

src/wasm/function-body-decoder-impl.h

@@ -2359,12 +2359,20 @@ class WasmFullDecoder : public WasmDecoder<validate> {
     return true;
   }
 
-  bool CheckSimdPostMvp(WasmOpcode opcode) {
+  bool CheckSimdFeatureFlagOpcode(WasmOpcode opcode) {
     if (!FLAG_wasm_simd_post_mvp && WasmOpcodes::IsSimdPostMvpOpcode(opcode)) {
       this->DecodeError(
           "simd opcode not available, enable with --wasm-simd-post-mvp");
       return false;
     }
+
+    if (!FLAG_experimental_wasm_relaxed_simd &&
+        WasmOpcodes::IsRelaxedSimdOpcode(opcode)) {
+      this->DecodeError(
+          "simd opcode not available, enable with --experimental-relaxed-simd");
+      return false;
+    }
+
     return true;
   }
 
@@ -3338,7 +3346,7 @@ class WasmFullDecoder : public WasmDecoder<validate> {
         this->pc_, &opcode_length);
     if (!VALIDATE(this->ok())) return 0;
     trace_msg->AppendOpcode(full_opcode);
-    if (!CheckSimdPostMvp(full_opcode)) {
+    if (!CheckSimdFeatureFlagOpcode(full_opcode)) {
       return 0;
     }
     return DecodeSimdOpcode(full_opcode, opcode_length);

src/wasm/wasm-opcodes-inl.h

@@ -545,7 +545,6 @@ constexpr bool WasmOpcodes::IsThrowingOpcode(WasmOpcode opcode) {
 constexpr bool WasmOpcodes::IsSimdPostMvpOpcode(WasmOpcode opcode) {
   switch (opcode) {
 #define CHECK_OPCODE(name, opcode, _) case kExpr##name:
-    FOREACH_SIMD_POST_MVP_OPCODE(CHECK_OPCODE)
     FOREACH_SIMD_POST_MVP_MEM_OPCODE(CHECK_OPCODE)
 #undef CHECK_OPCODE
     return true;
@@ -554,6 +553,18 @@ constexpr bool WasmOpcodes::IsSimdPostMvpOpcode(WasmOpcode opcode) {
   }
 }
 
+// static
+constexpr bool WasmOpcodes::IsRelaxedSimdOpcode(WasmOpcode opcode) {
+  switch (opcode) {
+#define CHECK_OPCODE(name, opcode, _) case kExpr##name:
+    FOREACH_RELAXED_SIMD_OPCODE(CHECK_OPCODE)
+#undef CHECK_OPCODE
+    return true;
+    default:
+      return false;
+  }
+}
+
 namespace impl {
 
 #define DECLARE_SIG_ENUM(name, ...) kSigEnum_##name,

src/wasm/wasm-opcodes.h

@@ -518,12 +518,12 @@ bool V8_EXPORT_PRIVATE IsJSCompatibleSignature(const FunctionSig* sig,
   V(PrefetchT, 0xfdc5, v_i)                 \
   V(PrefetchNT, 0xfdc6, v_i)
 
-#define FOREACH_SIMD_POST_MVP_OPCODE(V) \
-  V(F32x4Qfma, 0xfdaf, s_sss)           \
-  V(F32x4Qfms, 0xfdb0, s_sss)           \
-  V(F64x2Qfma, 0xfdcf, s_sss)           \
-  V(F64x2Qfms, 0xfdd0, s_sss)           \
-  V(F32x4RecipApprox, 0xfdd2, s_s)      \
+#define FOREACH_RELAXED_SIMD_OPCODE(V) \
+  V(F32x4Qfma, 0xfdaf, s_sss)          \
+  V(F32x4Qfms, 0xfdb0, s_sss)          \
+  V(F64x2Qfma, 0xfdcf, s_sss)          \
+  V(F64x2Qfms, 0xfdd0, s_sss)          \
+  V(F32x4RecipApprox, 0xfdd2, s_s)     \
   V(F32x4RecipSqrtApprox, 0xfdd3, s_s)
 
 #define FOREACH_SIMD_1_OPERAND_1_PARAM_OPCODE(V) \
@@ -546,7 +546,7 @@ bool V8_EXPORT_PRIVATE IsJSCompatibleSignature(const FunctionSig* sig,
 
 #define FOREACH_SIMD_0_OPERAND_OPCODE(V) \
   FOREACH_SIMD_MVP_0_OPERAND_OPCODE(V)   \
-  FOREACH_SIMD_POST_MVP_OPCODE(V)
+  FOREACH_RELAXED_SIMD_OPCODE(V)
 
 #define FOREACH_SIMD_1_OPERAND_OPCODE(V)   \
   FOREACH_SIMD_1_OPERAND_1_PARAM_OPCODE(V) \
@@ -797,6 +797,7 @@ class V8_EXPORT_PRIVATE WasmOpcodes {
   static constexpr bool IsExternRefOpcode(WasmOpcode);
   static constexpr bool IsThrowingOpcode(WasmOpcode);
   static constexpr bool IsSimdPostMvpOpcode(WasmOpcode);
+  static constexpr bool IsRelaxedSimdOpcode(WasmOpcode);
   // Check whether the given opcode always jumps, i.e. all instructions after
   // this one in the current block are dead. Returns false for |end|.
   static constexpr bool IsUnconditionalJump(WasmOpcode);

test/cctest/wasm/test-run-wasm-simd.cc

@@ -388,6 +388,22 @@ bool ExpectFused(TestExecutionTier tier) {
   void RunWasm_##name##_Impl(LowerSimd lower_simd,                        \
                              TestExecutionTier execution_tier)
 
+// Use this for experimental relaxed-simd opcodes.
+#define WASM_RELAXED_SIMD_TEST(name)                                      \
+  void RunWasm_##name##_Impl(LowerSimd lower_simd,                        \
+                             TestExecutionTier execution_tier);           \
+  TEST(RunWasm_##name##_turbofan) {                                       \
+    if (!CpuFeatures::SupportsWasmSimd128()) return;                      \
+    EXPERIMENTAL_FLAG_SCOPE(relaxed_simd);                                \
+    RunWasm_##name##_Impl(kNoLowerSimd, TestExecutionTier::kTurbofan);    \
+  }                                                                       \
+  TEST(RunWasm_##name##_interpreter) {                                    \
+    EXPERIMENTAL_FLAG_SCOPE(relaxed_simd);                                \
+    RunWasm_##name##_Impl(kNoLowerSimd, TestExecutionTier::kInterpreter); \
+  }                                                                       \
+  void RunWasm_##name##_Impl(LowerSimd lower_simd,                        \
+                             TestExecutionTier execution_tier)
+
 // Returns true if the platform can represent the result.
 template <typename T>
 bool PlatformCanRepresent(T x) {
@@ -627,12 +643,12 @@ WASM_SIMD_TEST(F32x4Sqrt) {
   RunF32x4UnOpTest(execution_tier, lower_simd, kExprF32x4Sqrt, std::sqrt);
 }
 
-WASM_SIMD_TEST_POST_MVP(F32x4RecipApprox) {
+WASM_RELAXED_SIMD_TEST(F32x4RecipApprox) {
   RunF32x4UnOpTest(execution_tier, lower_simd, kExprF32x4RecipApprox,
                    base::Recip, false /* !exact */);
 }
 
-WASM_SIMD_TEST_POST_MVP(F32x4RecipSqrtApprox) {
+WASM_RELAXED_SIMD_TEST(F32x4RecipSqrtApprox) {
   RunF32x4UnOpTest(execution_tier, lower_simd, kExprF32x4RecipSqrtApprox,
                    base::RecipSqrt, false /* !exact */);
 }
@@ -785,7 +801,7 @@ WASM_SIMD_TEST(F32x4Le) {
 }
 
 #if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X
-WASM_SIMD_TEST_POST_MVP(F32x4Qfma) {
+WASM_RELAXED_SIMD_TEST(F32x4Qfma) {
   WasmRunner<int32_t, float, float, float> r(execution_tier, lower_simd);
   // Set up global to hold mask output.
   float* g = r.builder().AddGlobal<float>(kWasmS128);
@@ -809,7 +825,7 @@ WASM_SIMD_TEST_POST_MVP(F32x4Qfma) {
   }
 }
 
-WASM_SIMD_TEST_POST_MVP(F32x4Qfms) {
+WASM_RELAXED_SIMD_TEST(F32x4Qfms) {
   WasmRunner<int32_t, float, float, float> r(execution_tier, lower_simd);
   // Set up global to hold mask output.
   float* g = r.builder().AddGlobal<float>(kWasmS128);
@@ -1509,7 +1525,7 @@ WASM_SIMD_TEST(I64x2Mul) {
 }
 
 #if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X
-WASM_SIMD_TEST_POST_MVP(F64x2Qfma) {
+WASM_RELAXED_SIMD_TEST(F64x2Qfma) {
   WasmRunner<int32_t, double, double, double> r(execution_tier, lower_simd);
   // Set up global to hold mask output.
   double* g = r.builder().AddGlobal<double>(kWasmS128);
@@ -1533,7 +1549,7 @@ WASM_SIMD_TEST_POST_MVP(F64x2Qfma) {
   }
 }
 
-WASM_SIMD_TEST_POST_MVP(F64x2Qfms) {
+WASM_RELAXED_SIMD_TEST(F64x2Qfms) {
   WasmRunner<int32_t, double, double, double> r(execution_tier, lower_simd);
   // Set up global to hold mask output.
   double* g = r.builder().AddGlobal<double>(kWasmS128);