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Commit 70fd0686 authored by Milad Farazmand's avatar Milad Farazmand Committed by Commit Bot
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s390: [wasm-simd] Implement simd binary operations 

Change-Id: I2733dbbe77ac731a61c9a8dfcf6ed52a9ace4eaf
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1946687Reviewed-by: 's avatarJoran Siu <joransiu@ca.ibm.com>
Reviewed-by: 's avatarJunliang Yan <jyan@ca.ibm.com>
Reviewed-by: 's avatarMilad Farazmand <miladfar@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#65416}
parent 4cfa97f6
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Showing with 180 additions and 28 deletions
src/compiler/backend/s390/code-generator-s390.cc
View file @ 70fd0686
......@@ -2884,6 +2884,126 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kS390_Word64AtomicCompareExchangeUint64:
ASSEMBLE_ATOMIC64_COMP_EXCHANGE_WORD64();
break;
// vector binops
case kS390_F32x4Add: {
__ vfa(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_F32x4AddHoriz: {
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
DoubleRegister tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
DoubleRegister tempFPReg2 = i.ToSimd128Register(instr->TempAt(1));
constexpr int shift_bits = 32;
// generate first operand
__ vpk(dst, src1, src0, Condition(0), Condition(0), Condition(3));
// generate second operand
__ vesrl(tempFPReg1, src0, MemOperand(r0, shift_bits), Condition(3));
__ vesrl(tempFPReg2, src1, MemOperand(r0, shift_bits), Condition(3));
__ vpk(kScratchDoubleReg, tempFPReg2, tempFPReg1, Condition(0),
Condition(0), Condition(3));
// add the operands
__ vfa(dst, kScratchDoubleReg, dst, Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_F32x4Sub: {
__ vfs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_F32x4Mul: {
__ vfm(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_I32x4Add: {
__ va(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_I32x4AddHoriz: {
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ vs(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg,
Condition(0), Condition(0), Condition(2));
__ vsumg(dst, src0, kScratchDoubleReg, Condition(0), Condition(0),
Condition(2));
__ vsumg(kScratchDoubleReg, src1, kScratchDoubleReg, Condition(0),
Condition(0), Condition(2));
__ vpk(dst, kScratchDoubleReg, dst, Condition(0), Condition(0),
Condition(3));
break;
}
case kS390_I32x4Sub: {
__ vs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_I32x4Mul: {
__ vml(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_I16x8Add: {
__ va(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(1));
break;
}
case kS390_I16x8AddHoriz: {
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ vs(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg,
Condition(0), Condition(0), Condition(1));
__ vsum(dst, src0, kScratchDoubleReg, Condition(0), Condition(0),
Condition(1));
__ vsum(kScratchDoubleReg, src1, kScratchDoubleReg, Condition(0),
Condition(0), Condition(1));
__ vpk(dst, kScratchDoubleReg, dst, Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_I16x8Sub: {
__ vs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(1));
break;
}
case kS390_I16x8Mul: {
__ vml(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(1));
break;
}
case kS390_I8x16Add: {
__ va(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(0));
break;
}
case kS390_I8x16Sub: {
__ vs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(0));
break;
}
case kS390_I8x16Mul: {
__ vml(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(0));
break;
}
default:
UNREACHABLE();
}
......
src/compiler/backend/s390/instruction-codes-s390.h
View file @ 70fd0686
......@@ -197,6 +197,21 @@ namespace compiler {
V(S390_Word64AtomicXorUint16) \
V(S390_Word64AtomicXorUint32) \
V(S390_Word64AtomicXorUint64) \
V(S390_F32x4Add) \
V(S390_F32x4AddHoriz) \
V(S390_F32x4Sub) \
V(S390_F32x4Mul) \
V(S390_I32x4Add) \
V(S390_I32x4AddHoriz) \
V(S390_I32x4Sub) \
V(S390_I32x4Mul) \
V(S390_I16x8Add) \
V(S390_I16x8AddHoriz) \
V(S390_I16x8Sub) \
V(S390_I16x8Mul) \
V(S390_I8x16Add) \
V(S390_I8x16Sub) \
V(S390_I8x16Mul) \
V(S390_StoreSimd128) \
V(S390_LoadSimd128)
......
src/compiler/backend/s390/instruction-scheduler-s390.cc
View file @ 70fd0686
......@@ -143,6 +143,21 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_CompressSigned:
case kS390_CompressPointer:
case kS390_CompressAny:
case kS390_F32x4Add:
case kS390_F32x4AddHoriz:
case kS390_F32x4Sub:
case kS390_F32x4Mul:
case kS390_I32x4Add:
case kS390_I32x4AddHoriz:
case kS390_I32x4Sub:
case kS390_I32x4Mul:
case kS390_I16x8Add:
case kS390_I16x8AddHoriz:
case kS390_I16x8Sub:
case kS390_I16x8Mul:
case kS390_I8x16Add:
case kS390_I8x16Sub:
case kS390_I8x16Mul:
return kNoOpcodeFlags;
case kS390_LoadWordS8:
......
src/compiler/backend/s390/instruction-selector-s390.cc
View file @ 70fd0686
......@@ -2528,20 +2528,44 @@ SIMD_VISIT_EXTRACT_LANE(I8x16, U)
SIMD_VISIT_EXTRACT_LANE(I8x16, S)
#undef SIMD_VISIT_EXTRACT_LANE
#define SIMD_BINOP_LIST(V) \
V(F32x4Add) \
V(F32x4AddHoriz) \
V(F32x4Sub) \
V(F32x4Mul) \
V(I32x4Add) \
V(I32x4AddHoriz) \
V(I32x4Sub) \
V(I32x4Mul) \
V(I16x8Add) \
V(I16x8AddHoriz) \
V(I16x8Sub) \
V(I16x8Mul) \
V(I8x16Add) \
V(I8x16Sub) \
V(I8x16Mul)
#define VISIT_SIMD_BINOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \
InstructionOperand temps[] = {g.TempSimd128Register(), \
g.TempSimd128Register()}; \
Emit(kS390_##Opcode, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0)), \
g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps); \
}
SIMD_BINOP_LIST(VISIT_SIMD_BINOP)
#undef VISIT_SIMD_BINOP
#undef SIMD_BINOP_LIST
void InstructionSelector::VisitI32x4Splat(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4ReplaceLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4Add(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4Sub(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4Shl(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4ShrS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4Mul(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4MaxS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4MinS(Node* node) { UNIMPLEMENTED(); }
......@@ -2576,20 +2600,14 @@ void InstructionSelector::VisitI16x8ShrS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8ShrU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8Add(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8AddSaturateS(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8Sub(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8SubSaturateS(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8Mul(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8MinS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8MaxS(Node* node) { UNIMPLEMENTED(); }
......@@ -2626,14 +2644,10 @@ void InstructionSelector::VisitI8x16Splat(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16ReplaceLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16Add(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16AddSaturateS(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16Sub(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16SubSaturateS(Node* node) {
UNIMPLEMENTED();
}
......@@ -2711,12 +2725,6 @@ void InstructionSelector::EmitPrepareResults(
}
}
void InstructionSelector::VisitF32x4Add(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Sub(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Mul(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Sqrt(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Div(Node* node) { UNIMPLEMENTED(); }
......@@ -2737,10 +2745,6 @@ void InstructionSelector::VisitF32x4RecipSqrtApprox(Node* node) {
void InstructionSelector::VisitF32x4RecipApprox(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4AddHoriz(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4AddHoriz(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8AddHoriz(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4SConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
......@@ -2822,8 +2826,6 @@ void InstructionSelector::VisitI8x16ShrS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16ShrU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16Mul(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS8x16Shuffle(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS8x16Swizzle(Node* node) { UNIMPLEMENTED(); }
......
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