[wasm simd] Implement F64x2Neg on x64

Bug: v8:8460
Change-Id: I3e649e1398be429b8aff5b57316e320f9ca5ae8f
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1703763
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#62817}

src/compiler/backend/instruction-selector.cc

@@ -1822,6 +1822,8 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd128(node), VisitF64x2ReplaceLane(node);
     case IrOpcode::kF64x2Abs:
       return MarkAsSimd128(node), VisitF64x2Abs(node);
+    case IrOpcode::kF64x2Neg:
+      return MarkAsSimd128(node), VisitF64x2Neg(node);
     case IrOpcode::kF64x2Eq:
       return MarkAsSimd128(node), VisitF64x2Eq(node);
     case IrOpcode::kF64x2Ne:
@@ -2552,6 +2554,7 @@ void InstructionSelector::VisitF64x2Splat(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitF64x2ExtractLane(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitF64x2ReplaceLane(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitF64x2Abs(Node* node) { UNIMPLEMENTED(); }
+void InstructionSelector::VisitF64x2Neg(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitF64x2Eq(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitF64x2Ne(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitF64x2Lt(Node* node) { UNIMPLEMENTED(); }

src/compiler/backend/x64/code-generator-x64.cc

@@ -2292,6 +2292,23 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       }
       break;
     }
+    case kX64F64x2Neg: {
+      // TODO(zhin): look at kSSEFloat64Neg instruction selection and codegen to
+      // avoid having 2 cases here, and potentially share code
+      CpuFeatureScope sse_scope(tasm(), SSE4_1);
+      XMMRegister dst = i.OutputSimd128Register();
+      XMMRegister src = i.InputSimd128Register(0);
+      if (dst == src) {
+        __ pcmpeqq(kScratchDoubleReg, kScratchDoubleReg);
+        __ psllq(kScratchDoubleReg, 63);
+        __ xorpd(dst, kScratchDoubleReg);
+      } else {
+        __ pcmpeqq(dst, dst);
+        __ psllq(dst, 63);
+        __ xorpd(dst, src);
+      }
+      break;
+    }
     case kX64F64x2Eq: {
       DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
       __ cmpeqpd(i.OutputSimd128Register(), i.InputSimd128Register(1));

src/compiler/backend/x64/instruction-codes-x64.h

@@ -162,6 +162,7 @@ namespace compiler {
   V(X64F64x2ExtractLane)                  \
   V(X64F64x2ReplaceLane)                  \
   V(X64F64x2Abs)                          \
+  V(X64F64x2Neg)                          \
   V(X64F64x2Eq)                           \
   V(X64F64x2Ne)                           \
   V(X64F64x2Lt)                           \

src/compiler/backend/x64/instruction-scheduler-x64.cc

@@ -128,6 +128,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kX64F64x2ExtractLane:
     case kX64F64x2ReplaceLane:
     case kX64F64x2Abs:
+    case kX64F64x2Neg:
     case kX64F64x2Eq:
     case kX64F64x2Ne:
     case kX64F64x2Lt:

src/compiler/backend/x64/instruction-selector-x64.cc

@@ -2661,6 +2661,7 @@ VISIT_ATOMIC_BINOP(Xor)
 
 #define SIMD_UNOP_LIST(V)   \
   V(F64x2Abs)               \
+  V(F64x2Neg)               \
   V(F32x4SConvertI32x4)     \
   V(F32x4Abs)               \
   V(F32x4Neg)               \

src/compiler/machine-operator.cc

@@ -247,6 +247,7 @@ MachineType AtomicOpType(Operator const* op) {
   V(Word32PairSar, Operator::kNoProperties, 3, 0, 2)                          \
   V(F64x2Splat, Operator::kNoProperties, 1, 0, 1)                             \
   V(F64x2Abs, Operator::kNoProperties, 1, 0, 1)                               \
+  V(F64x2Neg, Operator::kNoProperties, 1, 0, 1)                               \
   V(F64x2Eq, Operator::kCommutative, 2, 0, 1)                                 \
   V(F64x2Ne, Operator::kCommutative, 2, 0, 1)                                 \
   V(F64x2Lt, Operator::kNoProperties, 2, 0, 1)                                \

src/compiler/machine-operator.h

@@ -470,6 +470,7 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   // SIMD operators.
   const Operator* F64x2Splat();
   const Operator* F64x2Abs();
+  const Operator* F64x2Neg();
   const Operator* F64x2ExtractLane(int32_t);
   const Operator* F64x2ReplaceLane(int32_t);
   const Operator* F64x2Eq();

src/compiler/opcodes.h

@@ -744,6 +744,7 @@
   V(F64x2ExtractLane)           \
   V(F64x2ReplaceLane)           \
   V(F64x2Abs)                   \
+  V(F64x2Neg)                   \
   V(F64x2Eq)                    \
   V(F64x2Ne)                    \
   V(F64x2Lt)                    \

src/compiler/wasm-compiler.cc

@@ -3996,6 +3996,8 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode, Node* const* inputs) {
       return graph()->NewNode(mcgraph()->machine()->F64x2Splat(), inputs[0]);
     case wasm::kExprF64x2Abs:
       return graph()->NewNode(mcgraph()->machine()->F64x2Abs(), inputs[0]);
+    case wasm::kExprF64x2Neg:
+      return graph()->NewNode(mcgraph()->machine()->F64x2Neg(), inputs[0]);
     case wasm::kExprF64x2Eq:
       return graph()->NewNode(mcgraph()->machine()->F64x2Eq(), inputs[0],
                               inputs[1]);

src/wasm/wasm-interpreter.cc

@@ -2299,6 +2299,7 @@ class ThreadImpl {
     return true;                                \
   }
       UNOP_CASE(F64x2Abs, f64x2, float2, 2, std::abs(a))
+      UNOP_CASE(F64x2Neg, f64x2, float2, 2, -a)
       UNOP_CASE(F32x4Abs, f32x4, float4, 4, std::abs(a))
       UNOP_CASE(F32x4Neg, f32x4, float4, 4, -a)
       UNOP_CASE(F32x4RecipApprox, f32x4, float4, 4, base::Recip(a))

src/wasm/wasm-opcodes.cc

@@ -220,6 +220,7 @@ const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
     // SIMD opcodes.
     CASE_SIMD_OP(Splat, "splat")
     CASE_SIMD_OP(Neg, "neg")
+    CASE_F64x2_OP(Neg, "neg")
     CASE_I64x2_OP(Neg, "neg")
     CASE_SIMD_OP(Eq, "eq")
     CASE_F64x2_OP(Eq, "eq")

src/wasm/wasm-opcodes.h

@@ -386,6 +386,7 @@ bool IsJSCompatibleSignature(const FunctionSig* sig, bool hasBigIntFeature);
   V(F32x4Min, 0xfd9e, s_ss)              \
   V(F32x4Max, 0xfd9f, s_ss)              \
   V(F64x2Abs, 0xfda0, s_s)               \
+  V(F64x2Neg, 0xfda1, s_s)               \
   V(I32x4SConvertF32x4, 0xfdab, s_s)     \
   V(I32x4UConvertF32x4, 0xfdac, s_s)     \
   V(F32x4SConvertI32x4, 0xfdaf, s_s)     \

test/cctest/wasm/test-run-wasm-simd.cc

@@ -954,6 +954,10 @@ WASM_SIMD_TEST_NO_LOWERING(F64x2Abs) {
   RunF64x2UnOpTest(execution_tier, lower_simd, kExprF64x2Abs, std::abs);
 }
 
+WASM_SIMD_TEST_NO_LOWERING(F64x2Neg) {
+  RunF64x2UnOpTest(execution_tier, lower_simd, kExprF64x2Neg, Negate);
+}
+
 WASM_SIMD_TEST_NO_LOWERING(I64x2Splat) {
   WasmRunner<int32_t, int64_t> r(execution_tier, lower_simd);
   // Set up a global to hold output vector.