Commit 6b93449a authored by George Wort's avatar George Wort Committed by Commit Bot

[liftoff][arm] f32 rounding can use a C fallback

This allows f32 floor, ceil, trunc, and nearest_int to use a C fallback in
Liftoff in the same way that f64 rounding can.

Bug: v8:6600
Change-Id: I8b88d806633bcfe2d2dfac9defaf60e551bf21b1
Reviewed-on: https://chromium-review.googlesource.com/c/1353898
Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
Reviewed-by: 's avatarClemens Hammacher <clemensh@chromium.org>
Cr-Commit-Position: refs/heads/master@{#57909}
parent fcd0cf44
......@@ -621,10 +621,6 @@ UNIMPLEMENTED_FP_BINOP(f32_max)
UNIMPLEMENTED_FP_BINOP(f32_copysign)
UNIMPLEMENTED_FP_UNOP(f32_abs)
UNIMPLEMENTED_FP_UNOP(f32_neg)
UNIMPLEMENTED_FP_UNOP(f32_ceil)
UNIMPLEMENTED_FP_UNOP(f32_floor)
UNIMPLEMENTED_FP_UNOP(f32_trunc)
UNIMPLEMENTED_FP_UNOP(f32_nearest_int)
UNIMPLEMENTED_FP_UNOP(f32_sqrt)
FP64_BINOP(f64_add, vadd)
FP64_BINOP(f64_sub, vsub)
......@@ -795,6 +791,23 @@ void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister lhs,
BAILOUT("i64_shr");
}
bool LiftoffAssembler::emit_f32_ceil(DoubleRegister dst, DoubleRegister src) {
return false;
}
bool LiftoffAssembler::emit_f32_floor(DoubleRegister dst, DoubleRegister src) {
return false;
}
bool LiftoffAssembler::emit_f32_trunc(DoubleRegister dst, DoubleRegister src) {
return false;
}
bool LiftoffAssembler::emit_f32_nearest_int(DoubleRegister dst,
DoubleRegister src) {
return false;
}
bool LiftoffAssembler::emit_f64_ceil(DoubleRegister dst, DoubleRegister src) {
if (CpuFeatures::IsSupported(ARMv8)) {
CpuFeatureScope scope(this, ARMv8);
......
......@@ -372,6 +372,11 @@ void LiftoffAssembler::FillI64Half(Register, uint32_t half_index) {
void LiftoffAssembler::emit_##name(DoubleRegister dst, DoubleRegister src) { \
instruction(dst.S(), src.S()); \
}
#define FP32_UNOP_RETURN_TRUE(name, instruction) \
bool LiftoffAssembler::emit_##name(DoubleRegister dst, DoubleRegister src) { \
instruction(dst.S(), src.S()); \
return true; \
}
#define FP64_BINOP(name, instruction) \
void LiftoffAssembler::emit_##name(DoubleRegister dst, DoubleRegister lhs, \
DoubleRegister rhs) { \
......@@ -436,10 +441,10 @@ FP32_BINOP(f32_min, Fmin)
FP32_BINOP(f32_max, Fmax)
FP32_UNOP(f32_abs, Fabs)
FP32_UNOP(f32_neg, Fneg)
FP32_UNOP(f32_ceil, Frintp)
FP32_UNOP(f32_floor, Frintm)
FP32_UNOP(f32_trunc, Frintz)
FP32_UNOP(f32_nearest_int, Frintn)
FP32_UNOP_RETURN_TRUE(f32_ceil, Frintp)
FP32_UNOP_RETURN_TRUE(f32_floor, Frintm)
FP32_UNOP_RETURN_TRUE(f32_trunc, Frintz)
FP32_UNOP_RETURN_TRUE(f32_nearest_int, Frintn)
FP32_UNOP(f32_sqrt, Fsqrt)
FP64_BINOP(f64_add, Fadd)
FP64_BINOP(f64_sub, Fsub)
......
......@@ -1070,25 +1070,41 @@ void LiftoffAssembler::emit_f32_neg(DoubleRegister dst, DoubleRegister src) {
}
}
void LiftoffAssembler::emit_f32_ceil(DoubleRegister dst, DoubleRegister src) {
REQUIRE_CPU_FEATURE(SSE4_1);
roundss(dst, src, kRoundUp);
bool LiftoffAssembler::emit_f32_ceil(DoubleRegister dst, DoubleRegister src) {
if (CpuFeatures::IsSupported(SSE4_1)) {
CpuFeatureScope feature(this, SSE4_1);
roundss(dst, src, kRoundUp);
return true;
}
return false;
}
void LiftoffAssembler::emit_f32_floor(DoubleRegister dst, DoubleRegister src) {
REQUIRE_CPU_FEATURE(SSE4_1);
roundss(dst, src, kRoundDown);
bool LiftoffAssembler::emit_f32_floor(DoubleRegister dst, DoubleRegister src) {
if (CpuFeatures::IsSupported(SSE4_1)) {
CpuFeatureScope feature(this, SSE4_1);
roundss(dst, src, kRoundDown);
return true;
}
return false;
}
void LiftoffAssembler::emit_f32_trunc(DoubleRegister dst, DoubleRegister src) {
REQUIRE_CPU_FEATURE(SSE4_1);
roundss(dst, src, kRoundToZero);
bool LiftoffAssembler::emit_f32_trunc(DoubleRegister dst, DoubleRegister src) {
if (CpuFeatures::IsSupported(SSE4_1)) {
CpuFeatureScope feature(this, SSE4_1);
roundss(dst, src, kRoundToZero);
return true;
}
return false;
}
void LiftoffAssembler::emit_f32_nearest_int(DoubleRegister dst,
bool LiftoffAssembler::emit_f32_nearest_int(DoubleRegister dst,
DoubleRegister src) {
REQUIRE_CPU_FEATURE(SSE4_1);
roundss(dst, src, kRoundToNearest);
if (CpuFeatures::IsSupported(SSE4_1)) {
CpuFeatureScope feature(this, SSE4_1);
roundss(dst, src, kRoundToNearest);
return true;
}
return false;
}
void LiftoffAssembler::emit_f32_sqrt(DoubleRegister dst, DoubleRegister src) {
......
......@@ -497,10 +497,10 @@ class LiftoffAssembler : public TurboAssembler {
// f32 unops.
inline void emit_f32_abs(DoubleRegister dst, DoubleRegister src);
inline void emit_f32_neg(DoubleRegister dst, DoubleRegister src);
inline void emit_f32_ceil(DoubleRegister dst, DoubleRegister src);
inline void emit_f32_floor(DoubleRegister dst, DoubleRegister src);
inline void emit_f32_trunc(DoubleRegister dst, DoubleRegister src);
inline void emit_f32_nearest_int(DoubleRegister dst, DoubleRegister src);
inline bool emit_f32_ceil(DoubleRegister dst, DoubleRegister src);
inline bool emit_f32_floor(DoubleRegister dst, DoubleRegister src);
inline bool emit_f32_trunc(DoubleRegister dst, DoubleRegister src);
inline bool emit_f32_nearest_int(DoubleRegister dst, DoubleRegister src);
inline void emit_f32_sqrt(DoubleRegister dst, DoubleRegister src);
// f64 binops.
......
......@@ -660,10 +660,10 @@ class LiftoffCompiler {
CASE_I32_UNOP(I32Ctz, i32_ctz)
CASE_FLOAT_UNOP(F32Abs, F32, f32_abs)
CASE_FLOAT_UNOP(F32Neg, F32, f32_neg)
CASE_FLOAT_UNOP(F32Ceil, F32, f32_ceil)
CASE_FLOAT_UNOP(F32Floor, F32, f32_floor)
CASE_FLOAT_UNOP(F32Trunc, F32, f32_trunc)
CASE_FLOAT_UNOP(F32NearestInt, F32, f32_nearest_int)
CASE_FLOAT_UNOP_WITH_CFALLBACK(F32Ceil, F32, f32_ceil)
CASE_FLOAT_UNOP_WITH_CFALLBACK(F32Floor, F32, f32_floor)
CASE_FLOAT_UNOP_WITH_CFALLBACK(F32Trunc, F32, f32_trunc)
CASE_FLOAT_UNOP_WITH_CFALLBACK(F32NearestInt, F32, f32_nearest_int)
CASE_FLOAT_UNOP(F32Sqrt, F32, f32_sqrt)
CASE_FLOAT_UNOP(F64Abs, F64, f64_abs)
CASE_FLOAT_UNOP(F64Neg, F64, f64_neg)
......
......@@ -854,16 +854,21 @@ void LiftoffAssembler::emit_f64_copysign(DoubleRegister dst, DoubleRegister lhs,
void LiftoffAssembler::emit_##name(DoubleRegister dst, DoubleRegister src) { \
instruction(dst, src); \
}
#define FP_UNOP_RETURN_TRUE(name, instruction) \
bool LiftoffAssembler::emit_##name(DoubleRegister dst, DoubleRegister src) { \
instruction(dst, src); \
return true; \
}
FP_BINOP(f32_add, add_s)
FP_BINOP(f32_sub, sub_s)
FP_BINOP(f32_mul, mul_s)
FP_BINOP(f32_div, div_s)
FP_UNOP(f32_abs, abs_s)
FP_UNOP(f32_ceil, Ceil_s_s)
FP_UNOP(f32_floor, Floor_s_s)
FP_UNOP(f32_trunc, Trunc_s_s)
FP_UNOP(f32_nearest_int, Round_s_s)
FP_UNOP_RETURN_TRUE(f32_ceil, Ceil_s_s)
FP_UNOP_RETURN_TRUE(f32_floor, Floor_s_s)
FP_UNOP_RETURN_TRUE(f32_trunc, Trunc_s_s)
FP_UNOP_RETURN_TRUE(f32_nearest_int, Round_s_s)
FP_UNOP(f32_sqrt, sqrt_s)
FP_BINOP(f64_add, add_d)
FP_BINOP(f64_sub, sub_d)
......
......@@ -748,10 +748,10 @@ FP_BINOP(f32_sub, sub_s)
FP_BINOP(f32_mul, mul_s)
FP_BINOP(f32_div, div_s)
FP_UNOP(f32_abs, abs_s)
FP_UNOP(f32_ceil, Ceil_s_s)
FP_UNOP(f32_floor, Floor_s_s)
FP_UNOP(f32_trunc, Trunc_s_s)
FP_UNOP(f32_nearest_int, Round_s_s)
FP_UNOP_RETURN_TRUE(f32_ceil, Ceil_s_s)
FP_UNOP_RETURN_TRUE(f32_floor, Floor_s_s)
FP_UNOP_RETURN_TRUE(f32_trunc, Trunc_s_s)
FP_UNOP_RETURN_TRUE(f32_nearest_int, Round_s_s)
FP_UNOP(f32_sqrt, sqrt_s)
FP_BINOP(f64_add, add_d)
FP_BINOP(f64_sub, sub_d)
......
......@@ -169,10 +169,10 @@ UNIMPLEMENTED_FP_BINOP(f32_max)
UNIMPLEMENTED_FP_BINOP(f32_copysign)
UNIMPLEMENTED_FP_UNOP(f32_abs)
UNIMPLEMENTED_FP_UNOP(f32_neg)
UNIMPLEMENTED_FP_UNOP(f32_ceil)
UNIMPLEMENTED_FP_UNOP(f32_floor)
UNIMPLEMENTED_FP_UNOP(f32_trunc)
UNIMPLEMENTED_FP_UNOP(f32_nearest_int)
UNIMPLEMENTED_FP_UNOP_RETURN_TRUE(f32_ceil)
UNIMPLEMENTED_FP_UNOP_RETURN_TRUE(f32_floor)
UNIMPLEMENTED_FP_UNOP_RETURN_TRUE(f32_trunc)
UNIMPLEMENTED_FP_UNOP_RETURN_TRUE(f32_nearest_int)
UNIMPLEMENTED_FP_UNOP(f32_sqrt)
UNIMPLEMENTED_FP_BINOP(f64_add)
UNIMPLEMENTED_FP_BINOP(f64_sub)
......
......@@ -169,10 +169,10 @@ UNIMPLEMENTED_FP_BINOP(f32_max)
UNIMPLEMENTED_FP_BINOP(f32_copysign)
UNIMPLEMENTED_FP_UNOP(f32_abs)
UNIMPLEMENTED_FP_UNOP(f32_neg)
UNIMPLEMENTED_FP_UNOP(f32_ceil)
UNIMPLEMENTED_FP_UNOP(f32_floor)
UNIMPLEMENTED_FP_UNOP(f32_trunc)
UNIMPLEMENTED_FP_UNOP(f32_nearest_int)
UNIMPLEMENTED_FP_UNOP_RETURN_TRUE(f32_ceil)
UNIMPLEMENTED_FP_UNOP_RETURN_TRUE(f32_floor)
UNIMPLEMENTED_FP_UNOP_RETURN_TRUE(f32_trunc)
UNIMPLEMENTED_FP_UNOP_RETURN_TRUE(f32_nearest_int)
UNIMPLEMENTED_FP_UNOP(f32_sqrt)
UNIMPLEMENTED_FP_BINOP(f64_add)
UNIMPLEMENTED_FP_BINOP(f64_sub)
......
......@@ -933,25 +933,41 @@ void LiftoffAssembler::emit_f32_neg(DoubleRegister dst, DoubleRegister src) {
}
}
void LiftoffAssembler::emit_f32_ceil(DoubleRegister dst, DoubleRegister src) {
REQUIRE_CPU_FEATURE(SSE4_1);
Roundss(dst, src, kRoundUp);
bool LiftoffAssembler::emit_f32_ceil(DoubleRegister dst, DoubleRegister src) {
if (CpuFeatures::IsSupported(SSE4_1)) {
CpuFeatureScope feature(this, SSE4_1);
Roundss(dst, src, kRoundUp);
return true;
}
return false;
}
void LiftoffAssembler::emit_f32_floor(DoubleRegister dst, DoubleRegister src) {
REQUIRE_CPU_FEATURE(SSE4_1);
Roundss(dst, src, kRoundDown);
bool LiftoffAssembler::emit_f32_floor(DoubleRegister dst, DoubleRegister src) {
if (CpuFeatures::IsSupported(SSE4_1)) {
CpuFeatureScope feature(this, SSE4_1);
Roundss(dst, src, kRoundDown);
return true;
}
return false;
}
void LiftoffAssembler::emit_f32_trunc(DoubleRegister dst, DoubleRegister src) {
REQUIRE_CPU_FEATURE(SSE4_1);
Roundss(dst, src, kRoundToZero);
bool LiftoffAssembler::emit_f32_trunc(DoubleRegister dst, DoubleRegister src) {
if (CpuFeatures::IsSupported(SSE4_1)) {
CpuFeatureScope feature(this, SSE4_1);
Roundss(dst, src, kRoundToZero);
return true;
}
return false;
}
void LiftoffAssembler::emit_f32_nearest_int(DoubleRegister dst,
bool LiftoffAssembler::emit_f32_nearest_int(DoubleRegister dst,
DoubleRegister src) {
REQUIRE_CPU_FEATURE(SSE4_1);
Roundss(dst, src, kRoundToNearest);
if (CpuFeatures::IsSupported(SSE4_1)) {
CpuFeatureScope feature(this, SSE4_1);
Roundss(dst, src, kRoundToNearest);
return true;
}
return false;
}
void LiftoffAssembler::emit_f32_sqrt(DoubleRegister dst, DoubleRegister src) {
......
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