S390: Fix Div64 sequence + DLGR simulation

The CodeGenerator sequence for kS390_Div64 was incorrectly defaulting
to the 32-bit divide sequence.  That case has been fixed to use the
proper 64-bit divide (DSGR).

Fix bug in DLGR simulation where the register number was being used as
operands instead of the values in those registers.

R=jyan@ca.ibm.com,michael_dawson@ca.ibm.com,mbrandy@us.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1844563002

Cr-Commit-Position: refs/heads/master@{#35110}

src/compiler/s390/code-generator-s390.cc

@@ -1107,6 +1107,10 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       break;
 #if V8_TARGET_ARCH_S390X
     case kS390_Div64:
+      __ LoadRR(r1, i.InputRegister(0));
+      __ dsgr(r0, i.InputRegister(1));  // R1: Dividend
+      __ ltgr(i.OutputRegister(), r1);  // Copy R1: Quotient to output
+      break;
 #endif
     case kS390_Div32:
       __ LoadRR(r0, i.InputRegister(0));
@@ -1118,15 +1122,15 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
     case kS390_DivU64:
       __ LoadRR(r1, i.InputRegister(0));
       __ LoadImmP(r0, Operand::Zero());
-      __ dlgr(r0, i.InputRegister(1));  // R0:R1 = R1 / divisor -
-      __ ltgr(i.OutputRegister(), r1);  // Copy remainder to output reg
+      __ dlgr(r0, i.InputRegister(1));  // R0:R1: Dividend
+      __ ltgr(i.OutputRegister(), r1);  // Copy R1: Quotient to output
       break;
 #endif
     case kS390_DivU32:
       __ LoadRR(r0, i.InputRegister(0));
       __ srdl(r0, Operand(32));
-      __ dlr(r0, i.InputRegister(1));  // R0:R1 = R1 / divisor -
-      __ ltr(i.OutputRegister(), r1);  // Copy remainder to output reg
+      __ dlr(r0, i.InputRegister(1));  // R0:R1: Dividend
+      __ ltr(i.OutputRegister(), r1);  // Copy R1: Quotient to output
       break;
 
     case kS390_DivFloat:

src/s390/simulator-s390.cc

@@ -2720,11 +2720,11 @@ bool Simulator::DecodeFourByteArithmetic(Instruction* instr) {
       RREInstruction* rreinst = reinterpret_cast<RREInstruction*>(instr);
       int r1 = rreinst->R1Value();
       int r2 = rreinst->R2Value();
-      uint64_t r1_val = static_cast<uint64_t>(r1);
-      uint64_t r2_val = static_cast<uint64_t>(r2);
+      uint64_t r1_val = get_register(r1);
+      uint64_t r2_val = get_register(r2);
       DCHECK(r1 % 2 == 0);
       unsigned __int128 dividend = static_cast<unsigned __int128>(r1_val) << 64;
-      dividend += static_cast<uint64_t>(r1 + 1);
+      dividend += get_register(r1 + 1);
       uint64_t remainder = dividend % r2_val;
       uint64_t quotient = dividend / r2_val;
       r1_val = remainder;