Commit 690636c0 authored by Milad Fa's avatar Milad Fa Committed by Commit Bot

PPC [simd]: Implement vector population count

Change-Id: I88af87b611415753d1063d0b203f3c846fdecd57
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2778082Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#73579}
parent a33c8255
...@@ -2424,7 +2424,9 @@ using Instr = uint32_t; ...@@ -2424,7 +2424,9 @@ using Instr = uint32_t;
/* Vector Unpack Low Signed Byte */ \ /* Vector Unpack Low Signed Byte */ \
V(vupklsb, VUPKLSB, 0x1000028E) \ V(vupklsb, VUPKLSB, 0x1000028E) \
/* Vector Unpack High Signed Byte */ \ /* Vector Unpack High Signed Byte */ \
V(vupkhsb, VUPKHSB, 0x1000020E) V(vupkhsb, VUPKHSB, 0x1000020E) \
/* Vector Population Count Byte */ \
V(vpopcntb, VPOPCNTB, 0x10000703)
#define PPC_VX_OPCODE_UNUSED_LIST(V) \ #define PPC_VX_OPCODE_UNUSED_LIST(V) \
/* Decimal Add Modulo */ \ /* Decimal Add Modulo */ \
...@@ -2503,8 +2505,6 @@ using Instr = uint32_t; ...@@ -2503,8 +2505,6 @@ using Instr = uint32_t;
V(vpmsumh, VPMSUMH, 0x10000448) \ V(vpmsumh, VPMSUMH, 0x10000448) \
/* Vector Polynomial Multiply-Sum Word */ \ /* Vector Polynomial Multiply-Sum Word */ \
V(vpmsumw, VPMSUMW, 0x10000488) \ V(vpmsumw, VPMSUMW, 0x10000488) \
/* Vector Population Count Byte */ \
V(vpopcntb, VPOPCNTB, 0x10000703) \
/* Vector Population Count Doubleword */ \ /* Vector Population Count Doubleword */ \
V(vpopcntd, VPOPCNTD, 0x100007C3) \ V(vpopcntd, VPOPCNTD, 0x100007C3) \
/* Vector Population Count Halfword */ \ /* Vector Population Count Halfword */ \
......
...@@ -3823,6 +3823,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3823,6 +3823,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vinsertd(dst, kScratchSimd128Reg, Operand(lane_number)); __ vinsertd(dst, kScratchSimd128Reg, Operand(lane_number));
break; break;
} }
case kPPC_I8x16Popcnt: {
__ vpopcntb(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_StoreCompressTagged: { case kPPC_StoreCompressTagged: {
ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX); ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
break; break;
......
...@@ -386,6 +386,7 @@ namespace compiler { ...@@ -386,6 +386,7 @@ namespace compiler {
V(PPC_I8x16Shuffle) \ V(PPC_I8x16Shuffle) \
V(PPC_I8x16Swizzle) \ V(PPC_I8x16Swizzle) \
V(PPC_I8x16BitMask) \ V(PPC_I8x16BitMask) \
V(PPC_I8x16Popcnt) \
V(PPC_I64x2AllTrue) \ V(PPC_I64x2AllTrue) \
V(PPC_I32x4AllTrue) \ V(PPC_I32x4AllTrue) \
V(PPC_I16x8AllTrue) \ V(PPC_I16x8AllTrue) \
......
...@@ -309,6 +309,7 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -309,6 +309,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I8x16Shuffle: case kPPC_I8x16Shuffle:
case kPPC_I8x16Swizzle: case kPPC_I8x16Swizzle:
case kPPC_I8x16BitMask: case kPPC_I8x16BitMask:
case kPPC_I8x16Popcnt:
case kPPC_I64x2AllTrue: case kPPC_I64x2AllTrue:
case kPPC_I32x4AllTrue: case kPPC_I32x4AllTrue:
case kPPC_I16x8AllTrue: case kPPC_I16x8AllTrue:
......
...@@ -2293,6 +2293,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { ...@@ -2293,6 +2293,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8Abs) \ V(I16x8Abs) \
V(I8x16Neg) \ V(I8x16Neg) \
V(I8x16Abs) \ V(I8x16Abs) \
V(I8x16Popcnt) \
V(I16x8SConvertI8x16Low) \ V(I16x8SConvertI8x16Low) \
V(I16x8SConvertI8x16High) \ V(I16x8SConvertI8x16High) \
V(I16x8UConvertI8x16Low) \ V(I16x8UConvertI8x16Low) \
...@@ -2489,7 +2490,6 @@ void InstructionSelector::VisitS128Const(Node* node) { ...@@ -2489,7 +2490,6 @@ void InstructionSelector::VisitS128Const(Node* node) {
} }
} }
void InstructionSelector::VisitI8x16Popcnt(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2GtS(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI64x2GtS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2GeS(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI64x2GeS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Abs(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI64x2Abs(Node* node) { UNIMPLEMENTED(); }
......
...@@ -4842,6 +4842,17 @@ void Simulator::ExecuteGeneric(Instruction* instr) { ...@@ -4842,6 +4842,17 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
break; break;
} }
#undef VECTOR_ROUNDING_AVERAGE #undef VECTOR_ROUNDING_AVERAGE
case VPOPCNTB: {
int t = instr->RTValue();
int b = instr->RBValue();
FOR_EACH_LANE(i, uint8_t) {
set_simd_register_by_lane<uint8_t>(
t, i,
base::bits::CountPopulation(
get_simd_register_by_lane<uint8_t>(b, i)));
}
break;
}
#undef FOR_EACH_LANE #undef FOR_EACH_LANE
#undef DECODE_VX_INSTRUCTION #undef DECODE_VX_INSTRUCTION
#undef GET_ADDRESS #undef GET_ADDRESS
......
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