S390: [wasm] Int64Lowering of Int64Sub.

    Port 33c08596

    Original commit message:
        Int64Sub is lowered to a new turbofan operator, Int32SubPair. The new
        operator takes 4 inputs an generates 2 outputs. The inputs are the low
        word of the left input, high word of the left input, the low word of the
        right input, and high word of the right input. The ouputs are the low
        and high word of the result of the subtraction.

        The implementation is very similar to the implementation of Int64Add.

R=ahaas@chromium.org, joransiu@ca.ibm.com, michael_dawson@ca.ibm.com, mbrandy@us.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1807243002

Cr-Commit-Position: refs/heads/master@{#34865}

src/compiler/s390/code-generator-s390.cc

@@ -872,6 +872,16 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       __ AddLogicalWithCarry32(i.OutputRegister(1), i.InputRegister(1),
                                i.InputRegister(3));
       break;
+    case kS390_SubPair:
+      // i.InputRegister(0) ... left low word.
+      // i.InputRegister(1) ... left high word.
+      // i.InputRegister(2) ... right low word.
+      // i.InputRegister(3) ... right high word.
+      __ SubLogical32(i.OutputRegister(0), i.InputRegister(0),
+                      i.InputRegister(2));
+      __ SubLogicalWithBorrow32(i.OutputRegister(1), i.InputRegister(1),
+                                i.InputRegister(3));
+      break;
     case kS390_ShiftLeftPair:
       if (instr->InputAt(2)->IsImmediate()) {
         __ ShiftLeftPair(i.OutputRegister(0), i.OutputRegister(1),

src/compiler/s390/instruction-codes-s390.h

@@ -42,6 +42,7 @@ namespace compiler {
   V(S390_SubWithOverflow32)        \
   V(S390_SubFloat)                 \
   V(S390_SubDouble)                \
+  V(S390_SubPair)                  \
   V(S390_Mul32)                    \
   V(S390_Mul64)                    \
   V(S390_MulHigh32)                \

src/compiler/s390/instruction-scheduler-s390.cc

@@ -41,6 +41,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kS390_AddDouble:
     case kS390_Sub:
     case kS390_SubWithOverflow32:
+    case kS390_SubPair:
     case kS390_SubFloat:
     case kS390_SubDouble:
     case kS390_Mul32:

src/compiler/s390/instruction-selector-s390.cc

@@ -754,8 +754,9 @@ void InstructionSelector::VisitWord32Sar(Node* node) {
 }
 
 #if !V8_TARGET_ARCH_S390X
-void InstructionSelector::VisitInt32PairAdd(Node* node) {
-  S390OperandGenerator g(this);
+void VisitPairBinop(InstructionSelector* selector, ArchOpcode opcode,
+                    Node* node) {
+  S390OperandGenerator g(selector);
 
   // We use UseUniqueRegister here to avoid register sharing with the output
   // registers.
@@ -767,7 +768,15 @@ void InstructionSelector::VisitInt32PairAdd(Node* node) {
       g.DefineAsRegister(node),
       g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
 
-  Emit(kS390_AddPair, 2, outputs, 4, inputs);
+  selector->Emit(opcode, 2, outputs, 4, inputs);
+}
+
+void InstructionSelector::VisitInt32PairAdd(Node* node) {
+  VisitPairBinop(this, kS390_AddPair, node);
+}
+
+void InstructionSelector::VisitInt32PairSub(Node* node) {
+  VisitPairBinop(this, kS390_SubPair, node);
 }
 
 void VisitPairShift(InstructionSelector* selector, ArchOpcode opcode,

src/s390/assembler-s390.cc

@@ -2005,6 +2005,9 @@ void Assembler::sly(Register r1, const MemOperand& opnd) {
 // Subtract Logical Register-Register (32)
 void Assembler::slr(Register r1, Register r2) { rr_form(SLR, r1, r2); }
 
+// Subtract Logical With Borrow Register-Register (32)
+void Assembler::slbr(Register r1, Register r2) { rre_form(SLBR, r1, r2); }
+
 // Subtract Logical Register-Register-Register (32)
 void Assembler::slrk(Register r1, Register r2, Register r3) {
   rrf1_form(SLRK, r1, r2, r3);

src/s390/assembler-s390.h

@@ -1032,6 +1032,7 @@ class Assembler : public AssemblerBase {
   void sly(Register r1, const MemOperand& opnd);
   void slr(Register r1, Register r2);
   void slrk(Register r1, Register r2, Register r3);
+  void slbr(Register r1, Register r2);
 
   // 64-bit Subtract Logical Instructions
   void slg(Register r1, const MemOperand& opnd);

src/s390/disasm-s390.cc

@@ -781,6 +781,9 @@ bool Decoder::DecodeFourByte(Instruction* instr) {
     case SLGR:
       Format(instr, "slgr\t'r5,'r6");
       break;
+    case SLBR:
+      Format(instr, "slbr\t'r5,'r6");
+      break;
     case DLR:
       Format(instr, "dlr\t'r1,'r2");
       break;

src/s390/macro-assembler-s390.cc

@@ -4076,6 +4076,42 @@ void MacroAssembler::AddLogicalP(Register dst, const MemOperand& opnd) {
 //  Subtract Instructions
 //----------------------------------------------------------------------------
 
+// Subtract Logical With Carry 32-bit (Register dst = Register src1 - Register
+// src2)
+void MacroAssembler::SubLogicalWithBorrow32(Register dst, Register src1,
+                                            Register src2) {
+  if (!dst.is(src2) && !dst.is(src1)) {
+    lr(dst, src1);
+    slbr(dst, src2);
+  } else if (!dst.is(src2)) {
+    // dst == src1
+    DCHECK(dst.is(src1));
+    slbr(dst, src2);
+  } else {
+    // dst == src2
+    DCHECK(dst.is(src2));
+    lr(r0, dst);
+    SubLogicalWithBorrow32(dst, src1, r0);
+  }
+}
+
+// Subtract Logical 32-bit (Register dst = Register src1 - Register src2)
+void MacroAssembler::SubLogical32(Register dst, Register src1, Register src2) {
+  if (!dst.is(src2) && !dst.is(src1)) {
+    lr(dst, src1);
+    slr(dst, src2);
+  } else if (!dst.is(src2)) {
+    // dst == src1
+    DCHECK(dst.is(src1));
+    slr(dst, src2);
+  } else {
+    // dst == src2
+    DCHECK(dst.is(src2));
+    lr(r0, dst);
+    SubLogical32(dst, src1, r0);
+  }
+}
+
 // Subtract 32-bit (Register dst = Register dst - Immediate opnd)
 void MacroAssembler::Sub32(Register dst, const Operand& imm) {
   Add32(dst, Operand(-(imm.imm_)));

src/s390/macro-assembler-s390.h

@@ -296,6 +296,10 @@ class MacroAssembler : public Assembler {
   void SubLogical(Register dst, const MemOperand& opnd);
   void SubLogicalP(Register dst, const MemOperand& opnd);
   void SubLogicalP_ExtendSrc(Register dst, const MemOperand& opnd);
+  // Subtract Logical 32-bit
+  void SubLogical32(Register dst, Register src1, Register src2);
+  // Subtract Logical With Borrow 32-bit
+  void SubLogicalWithBorrow32(Register dst, Register src1, Register src2);
 
   // Multiply
   void MulP(Register dst, const Operand& opnd);