Commit 67113424 authored by Nico Weber's avatar Nico Weber Committed by V8 LUCI CQ

Fix -Wunreachable-code-aggressive warnings in arm and arm64 code

Like https://chromium-review.googlesource.com/c/v8/v8/+/2994804, but
for arm and arm64.

Bug: chromium:1066980
Change-Id: I5f3ac0d64a5031a62d4923d55a89f1d4e88cbc8b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3103905
Auto-Submit: Nico Weber <thakis@chromium.org>
Commit-Queue: Jakob Gruber <jgruber@chromium.org>
Reviewed-by: 's avatarJakob Gruber <jgruber@chromium.org>
Cr-Commit-Position: refs/heads/main@{#76374}
parent a9561d16
......@@ -676,7 +676,6 @@ int Decoder::FormatOption(Instruction* instr, const char* format) {
}
default: {
UNREACHABLE();
return -1;
}
}
out_buffer_pos_ +=
......@@ -787,7 +786,6 @@ void Decoder::DecodeType01(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else {
// strex
......@@ -808,7 +806,6 @@ void Decoder::DecodeType01(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
}
} else {
......@@ -853,7 +850,6 @@ void Decoder::DecodeType01(Instruction* instr) {
default: {
// The PU field is a 2-bit field.
UNREACHABLE();
break;
}
}
} else {
......@@ -894,7 +890,6 @@ void Decoder::DecodeType01(Instruction* instr) {
default: {
// The PU field is a 2-bit field.
UNREACHABLE();
break;
}
}
return;
......@@ -1030,7 +1025,6 @@ void Decoder::DecodeType01(Instruction* instr) {
default: {
// The Opcode field is a 4-bit field.
UNREACHABLE();
break;
}
}
}
......@@ -1107,10 +1101,8 @@ void Decoder::DecodeType3(Instruction* instr) {
break;
case 1:
UNREACHABLE();
break;
case 2:
UNREACHABLE();
break;
case 3:
Format(instr, "usat 'rd, #'imm05@16, 'rm'shift_sat");
break;
......@@ -1119,7 +1111,6 @@ void Decoder::DecodeType3(Instruction* instr) {
switch (instr->Bits(22, 21)) {
case 0:
UNREACHABLE();
break;
case 1:
if (instr->Bits(9, 6) == 1) {
if (instr->Bit(20) == 0) {
......@@ -1948,7 +1939,6 @@ void Decoder::DecodeFloatingPointDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE(); // Case analysis is exhaustive.
break;
}
} else if (instr->Opc1Value() == 0x4 && op2) {
// Floating-point minNum/maxNum.
......@@ -2002,7 +1992,6 @@ void Decoder::DecodeFloatingPointDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE(); // Case analysis is exhaustive.
break;
}
} else {
Unknown(instr);
......@@ -2617,12 +2606,10 @@ const char* NameConverter::NameOfCPURegister(int reg) const {
const char* NameConverter::NameOfByteCPURegister(int reg) const {
UNREACHABLE(); // ARM does not have the concept of a byte register
return "nobytereg";
}
const char* NameConverter::NameOfXMMRegister(int reg) const {
UNREACHABLE(); // ARM does not have any XMM registers
return "noxmmreg";
}
const char* NameConverter::NameInCode(byte* addr) const {
......
......@@ -37,7 +37,6 @@ int EhFrameWriter::RegisterToDwarfCode(Register name) {
return kR0DwarfCode;
default:
UNIMPLEMENTED();
return -1;
}
}
......@@ -54,7 +53,6 @@ const char* EhFrameDisassembler::DwarfRegisterCodeToString(int code) {
return "lr";
default:
UNIMPLEMENTED();
return nullptr;
}
}
......
......@@ -3954,7 +3954,6 @@ int DisassemblingDecoder::SubstituteImmediateField(Instruction* instr,
}
default: {
UNIMPLEMENTED();
return 0;
}
}
}
......@@ -3997,7 +3996,6 @@ int DisassemblingDecoder::SubstituteImmediateField(Instruction* instr,
return 0;
}
UNIMPLEMENTED();
return 0;
}
case 'L': { // IVLSLane[0123] - suffix indicates access size shift.
AppendToOutput("%d", instr->NEONLSIndex(format[8] - '0'));
......@@ -4042,12 +4040,10 @@ int DisassemblingDecoder::SubstituteImmediateField(Instruction* instr,
return static_cast<int>(strlen("IVMIShiftAmt2"));
} else {
UNIMPLEMENTED();
return 0;
}
}
default: {
UNIMPLEMENTED();
return 0;
}
}
}
......@@ -4342,12 +4338,10 @@ const char* NameConverter::NameOfCPURegister(int reg) const {
const char* NameConverter::NameOfByteCPURegister(int reg) const {
UNREACHABLE(); // ARM64 does not have the concept of a byte register
return "nobytereg";
}
const char* NameConverter::NameOfXMMRegister(int reg) const {
UNREACHABLE(); // ARM64 does not have any XMM registers
return "noxmmreg";
}
const char* NameConverter::NameInCode(byte* addr) const {
......
......@@ -38,7 +38,6 @@ int EhFrameWriter::RegisterToDwarfCode(Register name) {
return kX0DwarfCode;
default:
UNIMPLEMENTED();
return -1;
}
}
......
......@@ -114,14 +114,10 @@ bool ArmDebugger::GetValue(const char* desc, int32_t* value) {
if (regnum != kNoRegister) {
*value = GetRegisterValue(regnum);
return true;
} else {
if (strncmp(desc, "0x", 2) == 0) {
}
if (strncmp(desc, "0x", 2) == 0)
return SScanF(desc + 2, "%x", reinterpret_cast<uint32_t*>(value)) == 1;
} else {
return SScanF(desc, "%u", reinterpret_cast<uint32_t*>(value)) == 1;
}
}
return false;
}
bool ArmDebugger::GetVFPSingleValue(const char* desc, float* value) {
......@@ -1192,7 +1188,6 @@ bool Simulator::ConditionallyExecute(Instruction* instr) {
default:
UNREACHABLE();
}
return false;
}
// Calculate and set the Negative and Zero flags.
......@@ -1314,7 +1309,6 @@ int32_t Simulator::GetShiftRm(Instruction* instr, bool* carry_out) {
// by immediate
if ((shift == ROR) && (shift_amount == 0)) {
UNIMPLEMENTED();
return result;
} else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
shift_amount = 32;
}
......@@ -1373,7 +1367,6 @@ int32_t Simulator::GetShiftRm(Instruction* instr, bool* carry_out) {
default: {
UNREACHABLE();
break;
}
}
} else {
......@@ -1451,7 +1444,6 @@ int32_t Simulator::GetShiftRm(Instruction* instr, bool* carry_out) {
default: {
UNREACHABLE();
break;
}
}
}
......@@ -1486,7 +1478,6 @@ int32_t Simulator::ProcessPU(Instruction* instr, int num_regs, int reg_size,
switch (instr->PUField()) {
case da_x: {
UNIMPLEMENTED();
break;
}
case ia_x: {
*start_address = rn_val;
......@@ -1717,7 +1708,6 @@ void Simulator::SoftwareInterrupt(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
if (!stack_aligned) {
PrintF(" with unaligned stack %08x\n", get_register(sp));
......@@ -1769,7 +1759,6 @@ void Simulator::SoftwareInterrupt(Instruction* instr) {
}
default:
UNREACHABLE();
break;
}
if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
switch (redirection->type()) {
......@@ -1783,7 +1772,6 @@ void Simulator::SoftwareInterrupt(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
}
} else if (redirection->type() == ExternalReference::DIRECT_API_CALL) {
......@@ -2121,7 +2109,6 @@ void Simulator::DecodeType01(Instruction* instr) {
}
default:
UNREACHABLE();
break;
}
} else {
// The instruction is documented as strex rd, rt, [rn], but the
......@@ -2165,7 +2152,6 @@ void Simulator::DecodeType01(Instruction* instr) {
}
default:
UNREACHABLE();
break;
}
}
} else {
......@@ -2219,7 +2205,6 @@ void Simulator::DecodeType01(Instruction* instr) {
default: {
// The PU field is a 2-bit field.
UNREACHABLE();
break;
}
}
} else {
......@@ -2262,7 +2247,6 @@ void Simulator::DecodeType01(Instruction* instr) {
default: {
// The PU field is a 2-bit field.
UNREACHABLE();
break;
}
}
}
......@@ -2600,7 +2584,6 @@ void Simulator::DecodeType01(Instruction* instr) {
default: {
UNREACHABLE();
break;
}
}
}
......@@ -2680,7 +2663,6 @@ void Simulator::DecodeType3(Instruction* instr) {
DCHECK(!instr->HasW());
Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
UNIMPLEMENTED();
break;
}
case ia_x: {
if (instr->Bit(4) == 0) {
......@@ -2714,10 +2696,8 @@ void Simulator::DecodeType3(Instruction* instr) {
break;
case 1:
UNIMPLEMENTED();
break;
case 2:
UNIMPLEMENTED();
break;
case 3: {
// Usat.
int32_t sat_pos = instr->Bits(20, 16);
......@@ -2746,7 +2726,6 @@ void Simulator::DecodeType3(Instruction* instr) {
switch (instr->Bits(22, 21)) {
case 0:
UNIMPLEMENTED();
break;
case 1:
if (instr->Bits(9, 6) == 1) {
if (instr->Bit(20) == 0) {
......@@ -3442,7 +3421,6 @@ void Simulator::DecodeTypeVFP(Instruction* instr) {
}
default:
UNREACHABLE();
break;
}
set_neon_register(vd, q_data);
}
......@@ -4433,7 +4411,6 @@ void Simulator::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
}
default:
UNREACHABLE();
break;
}
break;
}
......@@ -4469,13 +4446,11 @@ void Simulator::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
}
default:
UNREACHABLE();
break;
}
break;
}
default:
UNREACHABLE();
break;
}
} else if (opc1 == 0 && (opc2 == 0b0100 || opc2 == 0b0101)) {
DCHECK_EQ(1, instr->Bit(6)); // Only support Q regs.
......@@ -4625,7 +4600,6 @@ void Simulator::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
break;
default:
UNIMPLEMENTED();
break;
}
}
} else if (opc1 == 0b01 && (opc2 & 0b0111) == 0b111) {
......@@ -4654,7 +4628,6 @@ void Simulator::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
break;
default:
UNIMPLEMENTED();
break;
}
}
} else if (opc1 == 0b10 && opc2 == 0b0001) {
......@@ -4674,7 +4647,6 @@ void Simulator::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else {
int Vd = instr->VFPDRegValue(kDoublePrecision);
......@@ -4692,7 +4664,6 @@ void Simulator::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
}
} else if (opc1 == 0b10 && (opc2 & 0b1110) == 0b0010) {
......@@ -4714,7 +4685,6 @@ void Simulator::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else {
// vuzp.<size> Qd, Qm.
......@@ -4730,7 +4700,6 @@ void Simulator::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
}
} else {
......@@ -4747,10 +4716,8 @@ void Simulator::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
break;
case Neon32:
UNIMPLEMENTED();
break;
default:
UNREACHABLE();
break;
}
} else {
// vuzp.<size> Dd, Dm.
......@@ -4763,10 +4730,8 @@ void Simulator::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
break;
case Neon32:
UNIMPLEMENTED();
break;
default:
UNREACHABLE();
break;
}
}
}
......@@ -4811,7 +4776,6 @@ void Simulator::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
}
case Neon64:
UNREACHABLE();
break;
}
} else if (opc1 == 0b10 && instr->Bit(10) == 1) {
// vrint<q>.<dt> <Dd>, <Dm>
......@@ -5078,7 +5042,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (!u && opc == 1 && sz == 2 && q && op1) {
// vmov Qd, Qm.
......@@ -5134,7 +5097,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (!u && opc == 3) {
// vcge/vcgt.s<size> Qd, Qm, Qn.
......@@ -5152,7 +5114,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (!u && opc == 4 && !op1) {
// vshl s<size> Qd, Qm, Qn.
......@@ -5172,7 +5133,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (!u && opc == 6) {
// vmin/vmax.s<size> Qd, Qm, Qn.
......@@ -5190,7 +5150,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (!u && opc == 8 && op1) {
// vtst.i<size> Qd, Qm, Qn.
......@@ -5207,7 +5166,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (!u && opc == 8 && !op1) {
// vadd.i<size> Qd, Qm, Qn.
......@@ -5241,7 +5199,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (!u && opc == 0xA) {
// vpmin/vpmax.s<size> Dd, Dm, Dn.
......@@ -5259,7 +5216,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (!u && opc == 0xB) {
// vpadd.i<size> Dd, Dm, Dn.
......@@ -5276,7 +5232,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (!u && opc == 0xD && !op1) {
float src1[4], src2[4];
......@@ -5347,7 +5302,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (u && opc == 1 && sz == 1 && op1) {
// vbsl.size Qd, Qm, Qn.
......@@ -5388,7 +5342,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (u && opc == 2 && op1) {
// vqsub.u<size> Qd, Qm, Qn.
......@@ -5405,7 +5358,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (u && opc == 3) {
// vcge/vcgt.u<size> Qd, Qm, Qn.
......@@ -5423,7 +5375,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (u && opc == 4 && !op1) {
// vshl u<size> Qd, Qm, Qn.
......@@ -5443,7 +5394,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (u && opc == 6) {
// vmin/vmax.u<size> Qd, Qm, Qn.
......@@ -5461,7 +5411,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (u && opc == 8 && !op1) {
// vsub.size Qd, Qm, Qn.
......@@ -5495,7 +5444,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (u && opc == 0xA) {
// vpmin/vpmax.u<size> Dd, Dm, Dn.
......@@ -5513,7 +5461,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (u && opc == 0xD && sz == 0 && q && op1) {
// vmul.f32 Qd, Qn, Qm
......@@ -5658,7 +5605,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNIMPLEMENTED();
break;
}
} else {
// vmovl signed
......@@ -5677,7 +5623,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNIMPLEMENTED();
break;
}
}
} else if (!u && imm3H_L != 0 && opc == 0b0101) {
......@@ -5721,7 +5666,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
} else if (u && imm3H_L != 0 && opc == 0b0101) {
// vsli.<size> Dd, Dm, shift
......@@ -5743,7 +5687,6 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE();
break;
}
}
}
......@@ -5807,7 +5750,6 @@ void Simulator::DecodeAdvancedSIMDLoadStoreMultipleStructures(
break;
default:
UNIMPLEMENTED();
break;
}
if (instr->Bit(21)) {
// vld1
......@@ -5993,7 +5935,6 @@ void Simulator::DecodeFloatingPointDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE(); // Case analysis is exhaustive.
break;
}
dd_value = canonicalizeNaN(dd_value);
set_d_register_from_double(vd, dd_value);
......@@ -6019,7 +5960,6 @@ void Simulator::DecodeFloatingPointDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE(); // Case analysis is exhaustive.
break;
}
sd_value = canonicalizeNaN(sd_value);
set_s_register_from_float(d, sd_value);
......@@ -6111,7 +6051,6 @@ void Simulator::DecodeFloatingPointDataProcessing(Instruction* instr) {
break;
default:
UNREACHABLE(); // Case analysis is exhaustive.
break;
}
if (instr->SzValue() == 0x1) {
int n = instr->VFPNRegValue(kDoublePrecision);
......@@ -6132,7 +6071,6 @@ void Simulator::DecodeFloatingPointDataProcessing(Instruction* instr) {
break;
default:
UNIMPLEMENTED();
break;
}
}
......@@ -6201,7 +6139,6 @@ void Simulator::InstructionDecode(Instruction* instr) {
}
default: {
UNIMPLEMENTED();
break;
}
}
}
......
......@@ -1517,7 +1517,6 @@ void Simulator::VisitPCRelAddressing(Instruction* instr) {
break;
case ADRP: // Not implemented in the assembler.
UNIMPLEMENTED();
break;
default:
UNREACHABLE();
}
......@@ -2212,7 +2211,6 @@ Simulator::TransactionSize Simulator::get_transaction_size(unsigned size) {
default:
UNREACHABLE();
}
return TransactionSize::None;
}
void Simulator::VisitLoadStoreAcquireRelease(Instruction* instr) {
......@@ -5210,7 +5208,6 @@ void Simulator::VisitNEONScalar2RegMisc(Instruction* instr) {
break;
default:
UNIMPLEMENTED();
break;
}
} else {
VectorFormat fpf = nfd.GetVectorFormat(nfd.FPScalarFormatMap());
......
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