[arm64][Liftoff] implement calls

Remove cp from cache register list

Bug: v8:6600
Change-Id: If17d4558e4f89dd620c757e2a8288658f1489435
Reviewed-on: https://chromium-review.googlesource.com/1047645Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
Commit-Queue: Vincent Belliard <vincent.belliard@arm.com>
Cr-Commit-Position: refs/heads/master@{#53114}

src/arm64/macro-assembler-arm64.cc

@@ -1377,8 +1377,7 @@ void TurboAssembler::Poke(const CPURegister& src, const Operand& offset) {
   Str(src, MemOperand(sp, offset));
 }
 
-
-void MacroAssembler::Peek(const CPURegister& dst, const Operand& offset) {
+void TurboAssembler::Peek(const CPURegister& dst, const Operand& offset) {
   if (offset.IsImmediate()) {
     DCHECK_GE(offset.ImmediateValue(), 0);
   } else if (emit_debug_code()) {

src/arm64/macro-assembler-arm64.h

@@ -1003,6 +1003,10 @@ class TurboAssembler : public Assembler {
   // be 16 byte aligned.
   void Poke(const CPURegister& src, const Operand& offset);
 
+  // Peek at a value on the stack, and put it in 'dst'. The offset is in bytes.
+  // The stack pointer must be aligned to 16 bytes.
+  void Peek(const CPURegister& dst, const Operand& offset);
+
   // Poke 'src1' and 'src2' onto the stack. The values written will be adjacent
   // with 'src2' at a higher address than 'src1'. The offset is in bytes. The
   // stack pointer must be 16 byte aligned.
@@ -1634,10 +1638,6 @@ class MacroAssembler : public TurboAssembler {
     std::vector<CPURegister> queued_;
   };
 
-  // Peek at a value on the stack, and put it in 'dst'. The offset is in bytes.
-  // The stack pointer must be aligned to 16 bytes.
-  void Peek(const CPURegister& dst, const Operand& offset);
-
   // Peek at two values on the stack, and put them in 'dst1' and 'dst2'. The
   // values peeked will be adjacent, with the value in 'dst2' being from a
   // higher address than 'dst1'. The offset is in bytes. The stack pointer must

src/wasm/baseline/arm64/liftoff-assembler-arm64.h

@@ -686,21 +686,61 @@ void LiftoffAssembler::CallC(wasm::FunctionSig* sig,
                              const LiftoffRegister* rets,
                              ValueType out_argument_type, int stack_bytes,
                              ExternalReference ext_ref) {
-  BAILOUT("CallC");
+  // The stack pointer is required to be quadword aligned.
+  int total_size = RoundUp(stack_bytes, kQuadWordSizeInBytes);
+  // Reserve space in the stack.
+  Claim(total_size, 1);
+
+  int arg_bytes = 0;
+  for (ValueType param_type : sig->parameters()) {
+    Poke(liftoff::GetRegFromType(*args++, param_type), arg_bytes);
+    arg_bytes += ValueTypes::MemSize(param_type);
+  }
+  DCHECK_LE(arg_bytes, stack_bytes);
+
+  // Pass a pointer to the buffer with the arguments to the C function.
+  Mov(x0, sp);
+
+  // Now call the C function.
+  constexpr int kNumCCallArgs = 1;
+  CallCFunction(ext_ref, kNumCCallArgs);
+
+  // Move return value to the right register.
+  const LiftoffRegister* next_result_reg = rets;
+  if (sig->return_count() > 0) {
+    DCHECK_EQ(1, sig->return_count());
+    constexpr Register kReturnReg = x0;
+    if (kReturnReg != next_result_reg->gp()) {
+      Move(*next_result_reg, LiftoffRegister(kReturnReg), sig->GetReturn(0));
+    }
+    ++next_result_reg;
+  }
+
+  // Load potential output value from the buffer on the stack.
+  if (out_argument_type != kWasmStmt) {
+    Peek(liftoff::GetRegFromType(*next_result_reg, out_argument_type), 0);
+  }
+
+  Drop(total_size, 1);
 }
 
 void LiftoffAssembler::CallNativeWasmCode(Address addr) {
-  BAILOUT("CallNativeWasmCode");
+  Call(addr, RelocInfo::WASM_CALL);
 }
 
 void LiftoffAssembler::CallRuntime(Zone* zone, Runtime::FunctionId fid) {
-  BAILOUT("CallRuntime");
+  // Set context to zero.
+  Mov(cp, xzr);
+  CallRuntimeDelayed(zone, fid);
 }
 
 void LiftoffAssembler::CallIndirect(wasm::FunctionSig* sig,
                                     compiler::CallDescriptor* call_descriptor,
                                     Register target) {
-  BAILOUT("CallIndirect");
+  // For Arm64, we have more cache registers than wasm parameters. That means
+  // that target will always be in a register.
+  DCHECK(target.IsValid());
+  Call(target);
 }
 
 void LiftoffAssembler::AllocateStackSlot(Register addr, uint32_t size) {

src/wasm/baseline/liftoff-assembler-defs.h

@@ -66,11 +66,11 @@ constexpr Register kNoParamRegister = t0;
 
 #elif V8_TARGET_ARCH_ARM64
 
-// x16: ip0, x17: ip1, x26: root, x29: fp, x30: lr, x31: xzr.
+// x16: ip0, x17: ip1, x26: root, x27: cp, x29: fp, x30: lr, x31: xzr.
 constexpr RegList kLiftoffAssemblerGpCacheRegs =
     CPURegister::ListOf<x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12,
                         x13, x14, x15, x18, x19, x20, x21, x22, x23, x24, x25,
-                        x27, x28>();
+                        x28>();
 
 // d15: fp_zero, d30-d31: macro-assembler scratch V Registers.
 constexpr RegList kLiftoffAssemblerFpCacheRegs =