[ptr-compr] Fix interaction with instruction selector and code generator

In x64 we can use the macro ASSEMBLE_MOVX.

In Arm64, we force the use of registers.

B

Cq-Include-Trybots: luci.v8.try:v8_linux64_pointer_compression_rel_ng,v8_linux64_arm64_pointer_compression_rel_ng
Bug: v8:8977
Change-Id: I98c6a12d28acca43a38a77dc3ee7af126edb64fe
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1545889
Auto-Submit: Santiago Aboy Solanes <solanes@chromium.org>
Commit-Queue: Jaroslav Sevcik <jarin@chromium.org>
Reviewed-by: Jaroslav Sevcik <jarin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#60518}

src/compiler/backend/arm64/instruction-selector-arm64.cc

@@ -1660,41 +1660,41 @@ void InstructionSelector::VisitChangeUint32ToUint64(Node* node) {
 void InstructionSelector::VisitChangeTaggedToCompressed(Node* node) {
   Arm64OperandGenerator g(this);
   Node* value = node->InputAt(0);
-  Emit(kArm64CompressAny, g.DefineAsRegister(node), g.Use(value));
+  Emit(kArm64CompressAny, g.DefineAsRegister(node), g.UseRegister(value));
 }
 
 void InstructionSelector::VisitChangeTaggedPointerToCompressedPointer(
     Node* node) {
   Arm64OperandGenerator g(this);
   Node* value = node->InputAt(0);
-  Emit(kArm64CompressPointer, g.DefineAsRegister(node), g.Use(value));
+  Emit(kArm64CompressPointer, g.DefineAsRegister(node), g.UseRegister(value));
 }
 
 void InstructionSelector::VisitChangeTaggedSignedToCompressedSigned(
     Node* node) {
   Arm64OperandGenerator g(this);
   Node* value = node->InputAt(0);
-  Emit(kArm64CompressSigned, g.DefineAsRegister(node), g.Use(value));
+  Emit(kArm64CompressSigned, g.DefineAsRegister(node), g.UseRegister(value));
 }
 
 void InstructionSelector::VisitChangeCompressedToTagged(Node* node) {
   Arm64OperandGenerator g(this);
   Node* const value = node->InputAt(0);
-  Emit(kArm64DecompressAny, g.DefineAsRegister(node), g.Use(value));
+  Emit(kArm64DecompressAny, g.DefineAsRegister(node), g.UseRegister(value));
 }
 
 void InstructionSelector::VisitChangeCompressedPointerToTaggedPointer(
     Node* node) {
   Arm64OperandGenerator g(this);
   Node* const value = node->InputAt(0);
-  Emit(kArm64DecompressPointer, g.DefineAsRegister(node), g.Use(value));
+  Emit(kArm64DecompressPointer, g.DefineAsRegister(node), g.UseRegister(value));
 }
 
 void InstructionSelector::VisitChangeCompressedSignedToTaggedSigned(
     Node* node) {
   Arm64OperandGenerator g(this);
   Node* const value = node->InputAt(0);
-  Emit(kArm64DecompressSigned, g.DefineAsRegister(node), g.Use(value));
+  Emit(kArm64DecompressSigned, g.DefineAsRegister(node), g.UseRegister(value));
 }
 
 void InstructionSelector::VisitTruncateInt64ToInt32(Node* node) {

src/compiler/backend/x64/code-generator-x64.cc

@@ -1953,18 +1953,18 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     }
     case kX64DecompressSigned: {
       CHECK(instr->HasOutput());
-      __ movsxlq(i.OutputRegister(), i.InputRegister(0));
+      ASSEMBLE_MOVX(movsxlq);
       break;
     }
     case kX64DecompressPointer: {
       CHECK(instr->HasOutput());
-      __ movsxlq(i.OutputRegister(), i.InputRegister(0));
+      ASSEMBLE_MOVX(movsxlq);
       __ addq(i.OutputRegister(), kRootRegister);
       break;
     }
     case kX64DecompressAny: {
       CHECK(instr->HasOutput());
-      __ movsxlq(i.OutputRegister(), i.InputRegister(0));
+      ASSEMBLE_MOVX(movsxlq);
       // TODO(solanes): Do branchful compute?
       // Branchlessly compute |masked_root|:
       STATIC_ASSERT((kSmiTagSize == 1) && (kSmiTag < 32));
@@ -1982,15 +1982,15 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     // TODO(solanes): We might get away with doing a no-op in these three cases.
     // The movl instruction is the conservative way for the moment.
     case kX64CompressSigned: {
-      __ movl(i.OutputRegister(), i.InputRegister(0));
+      ASSEMBLE_MOVX(movl);
       break;
     }
     case kX64CompressPointer: {
-      __ movl(i.OutputRegister(), i.InputRegister(0));
+      ASSEMBLE_MOVX(movl);
       break;
     }
     case kX64CompressAny: {
-      __ movl(i.OutputRegister(), i.InputRegister(0));
+      ASSEMBLE_MOVX(movl);
       break;
     }
     case kX64Movq: