ppc: [liftoff] implement i32/64_and/or/xor

Change-Id: Ib8acd67b66f54dad8f6653c83aff2369f4d3a482
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3036541Reviewed-by: Milad Fa <mfarazma@redhat.com>
Commit-Queue: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#75769}

src/codegen/ppc/macro-assembler-ppc.cc

@@ -2729,6 +2729,87 @@ void TurboAssembler::SubS32(Register dst, Register src, const Operand& value,
   extsw(dst, dst, r);
 }
 
+void TurboAssembler::AndU64(Register dst, Register src, const Operand& value,
+                            Register scratch, RCBit r) {
+  if (is_int16(value.immediate()) && r == SetRC) {
+    andi(dst, src, value);
+  } else {
+    mov(scratch, value);
+    and_(dst, src, scratch, r);
+  }
+}
+
+void TurboAssembler::AndU64(Register dst, Register src, Register value,
+                            RCBit r) {
+  and_(dst, src, value, r);
+}
+
+void TurboAssembler::OrU64(Register dst, Register src, const Operand& value,
+                           Register scratch, RCBit r) {
+  if (is_int16(value.immediate()) && r == SetRC) {
+    ori(dst, src, value);
+  } else {
+    mov(scratch, value);
+    orx(dst, src, scratch, r);
+  }
+}
+
+void TurboAssembler::OrU64(Register dst, Register src, Register value,
+                           RCBit r) {
+  orx(dst, src, value, r);
+}
+
+void TurboAssembler::XorU64(Register dst, Register src, const Operand& value,
+                            Register scratch, RCBit r) {
+  if (is_int16(value.immediate()) && r == SetRC) {
+    xori(dst, src, value);
+  } else {
+    mov(scratch, value);
+    xor_(dst, src, scratch, r);
+  }
+}
+
+void TurboAssembler::XorU64(Register dst, Register src, Register value,
+                            RCBit r) {
+  xor_(dst, src, value, r);
+}
+
+void TurboAssembler::AndU32(Register dst, Register src, const Operand& value,
+                            Register scratch, RCBit r) {
+  AndU64(dst, src, value, scratch, r);
+  extsw(dst, dst, r);
+}
+
+void TurboAssembler::AndU32(Register dst, Register src, Register value,
+                            RCBit r) {
+  AndU64(dst, src, value, r);
+  extsw(dst, dst, r);
+}
+
+void TurboAssembler::OrU32(Register dst, Register src, const Operand& value,
+                           Register scratch, RCBit r) {
+  OrU64(dst, src, value, scratch, r);
+  extsw(dst, dst, r);
+}
+
+void TurboAssembler::OrU32(Register dst, Register src, Register value,
+                           RCBit r) {
+  OrU64(dst, src, value, r);
+  extsw(dst, dst, r);
+}
+
+void TurboAssembler::XorU32(Register dst, Register src, const Operand& value,
+                            Register scratch, RCBit r) {
+  XorU64(dst, src, value, scratch, r);
+  extsw(dst, dst, r);
+}
+
+void TurboAssembler::XorU32(Register dst, Register src, Register value,
+                            RCBit r) {
+  XorU64(dst, src, value, r);
+  extsw(dst, dst, r);
+}
+
 void TurboAssembler::CmpS64(Register src1, Register src2, CRegister cr) {
   cmp(src1, src2, cr);
 }

src/codegen/ppc/macro-assembler-ppc.h

@@ -198,6 +198,25 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
               Register scratch = r0, RCBit r = LeaveRC);
   void SubS32(Register dst, Register src, Register value, RCBit r = LeaveRC);
 
+  void AndU64(Register dst, Register src, const Operand& value,
+              Register scratch = r0, RCBit r = SetRC);
+  void AndU64(Register dst, Register src, Register value, RCBit r = SetRC);
+  void OrU64(Register dst, Register src, const Operand& value,
+             Register scratch = r0, RCBit r = SetRC);
+  void OrU64(Register dst, Register src, Register value, RCBit r = SetRC);
+  void XorU64(Register dst, Register src, const Operand& value,
+              Register scratch = r0, RCBit r = SetRC);
+  void XorU64(Register dst, Register src, Register value, RCBit r = SetRC);
+  void AndU32(Register dst, Register src, const Operand& value,
+              Register scratch = r0, RCBit r = SetRC);
+  void AndU32(Register dst, Register src, Register value, RCBit r = SetRC);
+  void OrU32(Register dst, Register src, const Operand& value,
+             Register scratch = r0, RCBit r = SetRC);
+  void OrU32(Register dst, Register src, Register value, RCBit r = SetRC);
+  void XorU32(Register dst, Register src, const Operand& value,
+              Register scratch = r0, RCBit r = SetRC);
+  void XorU32(Register dst, Register src, Register value, RCBit r = SetRC);
+
   void Push(Register src) { push(src); }
   // Push a handle.
   void Push(Handle<HeapObject> handle);

src/wasm/baseline/ppc/liftoff-assembler-ppc.h

@@ -784,18 +784,10 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
   }
 
 UNIMPLEMENTED_I32_BINOP(i32_mul)
-UNIMPLEMENTED_I32_BINOP_I(i32_and)
-UNIMPLEMENTED_I32_BINOP_I(i32_or)
-UNIMPLEMENTED_I32_BINOP_I(i32_xor)
 UNIMPLEMENTED_I32_SHIFTOP(i32_shl)
 UNIMPLEMENTED_I32_SHIFTOP(i32_sar)
 UNIMPLEMENTED_I32_SHIFTOP(i32_shr)
 UNIMPLEMENTED_I64_BINOP(i64_mul)
-#ifdef V8_TARGET_ARCH_PPC64
-UNIMPLEMENTED_I64_BINOP_I(i64_and)
-UNIMPLEMENTED_I64_BINOP_I(i64_or)
-UNIMPLEMENTED_I64_BINOP_I(i64_xor)
-#endif
 UNIMPLEMENTED_I64_SHIFTOP(i64_shl)
 UNIMPLEMENTED_I64_SHIFTOP(i64_sar)
 UNIMPLEMENTED_I64_SHIFTOP(i64_shr)
@@ -886,7 +878,28 @@ UNOP_LIST(EMIT_UNOP_FUNCTION)
   V(i32_sub, SubS32, Register, Register, Register, , , , USE, , void)        \
   V(i32_add, AddS32, Register, Register, Register, , , , USE, , void)        \
   V(i32_addi, AddS32, Register, Register, int32_t, , , Operand, USE, , void) \
-  V(i32_subi, SubS32, Register, Register, int32_t, , , Operand, USE, , void)
+  V(i32_subi, SubS32, Register, Register, int32_t, , , Operand, USE, , void) \
+  V(i32_andi, AndU32, Register, Register, int32_t, , , Operand, SIGN_EXT, ,  \
+    void)                                                                    \
+  V(i32_ori, OrU32, Register, Register, int32_t, , , Operand, SIGN_EXT, ,    \
+    void)                                                                    \
+  V(i32_xori, XorU32, Register, Register, int32_t, , , Operand, SIGN_EXT, ,  \
+    void)                                                                    \
+  V(i32_and, AndU32, Register, Register, Register, , , , SIGN_EXT, , void)   \
+  V(i32_or, OrU32, Register, Register, Register, , , , SIGN_EXT, , void)     \
+  V(i32_xor, XorU32, Register, Register, Register, , , , SIGN_EXT, , void)   \
+  V(i64_and, AndU64, LiftoffRegister, LiftoffRegister, LiftoffRegister,      \
+    LFR_TO_REG, LFR_TO_REG, LFR_TO_REG, USE, , void)                         \
+  V(i64_or, OrU64, LiftoffRegister, LiftoffRegister, LiftoffRegister,        \
+    LFR_TO_REG, LFR_TO_REG, LFR_TO_REG, USE, , void)                         \
+  V(i64_xor, XorU64, LiftoffRegister, LiftoffRegister, LiftoffRegister,      \
+    LFR_TO_REG, LFR_TO_REG, LFR_TO_REG, USE, , void)                         \
+  V(i64_andi, AndU64, LiftoffRegister, LiftoffRegister, int32_t, LFR_TO_REG, \
+    LFR_TO_REG, Operand, USE, , void)                                        \
+  V(i64_ori, OrU64, LiftoffRegister, LiftoffRegister, int32_t, LFR_TO_REG,   \
+    LFR_TO_REG, Operand, USE, , void)                                        \
+  V(i64_xori, XorU64, LiftoffRegister, LiftoffRegister, int32_t, LFR_TO_REG, \
+    LFR_TO_REG, Operand, USE, , void)
 
 #define EMIT_BINOP_FUNCTION(name, instr, dtype, stype1, stype2, dcast, scast1, \
                             scast2, rcast, ret, return_type)                   \