Commit 650cc481 authored by sreten.kovacevic's avatar sreten.kovacevic Committed by Commit Bot

[Liftoff][mips] Implement eqz operations

Optimize initial implementation of i32_eqz and implement i64_eqz.

Bug: v8:6600
Change-Id: I695454a160fc57dc9981725583ed2f27c2c537db
Reviewed-on: https://chromium-review.googlesource.com/978207Reviewed-by: 's avatarIvica Bogosavljevic <ivica.bogosavljevic@mips.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Cr-Commit-Position: refs/heads/master@{#52189}
parent c69b03ba
......@@ -556,25 +556,7 @@ void LiftoffAssembler::emit_cond_jump(Condition cond, Label* label,
}
void LiftoffAssembler::emit_i32_eqz(Register dst, Register src) {
Label true_label;
if (dst != src) {
ori(dst, zero_reg, 0x1);
}
TurboAssembler::Branch(&true_label, eq, src, Operand(zero_reg));
// If not true, set on 0.
TurboAssembler::mov(dst, zero_reg);
if (dst != src) {
bind(&true_label);
} else {
Label end_label;
TurboAssembler::Branch(&end_label);
bind(&true_label);
ori(dst, zero_reg, 0x1);
bind(&end_label);
}
sltiu(dst, src, 1);
}
void LiftoffAssembler::emit_i32_set_cond(Condition cond, Register dst,
......@@ -601,7 +583,11 @@ void LiftoffAssembler::emit_i32_set_cond(Condition cond, Register dst,
}
void LiftoffAssembler::emit_i64_eqz(Register dst, LiftoffRegister src) {
BAILOUT("emit_i64_eqz");
Register tmp =
GetUnusedRegister(kGpReg, LiftoffRegList::ForRegs(src, dst)).gp();
sltiu(tmp, src.low_gp(), 1);
sltiu(dst, src.high_gp(), 1);
and_(dst, dst, tmp);
}
void LiftoffAssembler::emit_i64_set_cond(Condition cond, Register dst,
......
......@@ -450,25 +450,7 @@ void LiftoffAssembler::emit_cond_jump(Condition cond, Label* label,
}
void LiftoffAssembler::emit_i32_eqz(Register dst, Register src) {
Label true_label;
if (dst != src) {
ori(dst, zero_reg, 0x1);
}
TurboAssembler::Branch(&true_label, eq, src, Operand(zero_reg));
// If not true, set on 0.
TurboAssembler::mov(dst, zero_reg);
if (dst != src) {
bind(&true_label);
} else {
Label end_label;
TurboAssembler::Branch(&end_label);
bind(&true_label);
ori(dst, zero_reg, 0x1);
bind(&end_label);
}
sltiu(dst, src, 1);
}
void LiftoffAssembler::emit_i32_set_cond(Condition cond, Register dst,
......@@ -495,7 +477,7 @@ void LiftoffAssembler::emit_i32_set_cond(Condition cond, Register dst,
}
void LiftoffAssembler::emit_i64_eqz(Register dst, LiftoffRegister src) {
BAILOUT("emit_i64_eqz");
sltiu(dst, src.gp(), 1);
}
void LiftoffAssembler::emit_i64_set_cond(Condition cond, Register dst,
......
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