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Commit 6382a610 authored by jyan's avatar jyan Committed by Commit bot
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S390X: [turbofan] Word32 loads should be unsigned. 

TEST=cctest/test-run-load-store/*
R=joransiu@ca.ibm.com, mbrandy@us.ibm.com, michael_dawson@ca.ibm.com, bjaideep@ca.ibm.com
BUG=

S390: [interpreter] Heal closures when bytecode array is gone.

Port 5c8609de

Original commit message:

    This ensures the InterpreterEntryTrampoline heals code entry fields
    inside closures when being called without a valid bytecode array. This
    is preparatory work to allow removal of bytecode when switching some
    functions to other types of code.

R=mstarzinger@chromium.org, joransiu@ca.ibm.com, bjaideep@ca.ibm.com, michael_dawson@ca.ibm.com, mbrandy@us.ibm.com

BUG=v8:4280
LOG=N

Review URL: https://codereview.chromium.org/1916143002

Cr-Commit-Position: refs/heads/master@{#35779}
parent c07f0225
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Showing with 17 additions and 36 deletions
src/compiler/s390/code-generator-s390.cc
View file @ 6382a610
...@@ -237,15 +237,10 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { ...@@ -237,15 +237,10 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
#if V8_TARGET_ARCH_S390X #if V8_TARGET_ARCH_S390X
case kS390_Add: case kS390_Add:
case kS390_Sub: case kS390_Sub:
return lt;
#endif #endif
case kS390_AddWithOverflow32: case kS390_AddWithOverflow32:
case kS390_SubWithOverflow32: case kS390_SubWithOverflow32:
#if V8_TARGET_ARCH_S390X
return ne;
#else
return lt; return lt;
#endif
default: default:
break; break;
} }
...@@ -255,15 +250,10 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { ...@@ -255,15 +250,10 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
#if V8_TARGET_ARCH_S390X #if V8_TARGET_ARCH_S390X
case kS390_Add: case kS390_Add:
case kS390_Sub: case kS390_Sub:
return ge;
#endif #endif
case kS390_AddWithOverflow32: case kS390_AddWithOverflow32:
case kS390_SubWithOverflow32: case kS390_SubWithOverflow32:
#if V8_TARGET_ARCH_S390X
return eq;
#else
return ge; return ge;
#endif
default: default:
break; break;
} }
...@@ -333,16 +323,16 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { ...@@ -333,16 +323,16 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
} while (0) } while (0)
#if V8_TARGET_ARCH_S390X #if V8_TARGET_ARCH_S390X
#define ASSEMBLE_ADD_WITH_OVERFLOW32() \ #define ASSEMBLE_ADD_WITH_OVERFLOW32() \
do { \ do { \
ASSEMBLE_BINOP(AddP, AddP); \ ASSEMBLE_ADD_WITH_OVERFLOW(); \
__ TestIfInt32(i.OutputRegister(), r0); \ __ LoadAndTestP_ExtendSrc(kScratchReg, kScratchReg); \
} while (0) } while (0)
#define ASSEMBLE_SUB_WITH_OVERFLOW32() \ #define ASSEMBLE_SUB_WITH_OVERFLOW32() \
do { \ do { \
ASSEMBLE_BINOP(SubP, SubP); \ ASSEMBLE_SUB_WITH_OVERFLOW(); \
__ TestIfInt32(i.OutputRegister(), r0); \ __ LoadAndTestP_ExtendSrc(kScratchReg, kScratchReg); \
} while (0) } while (0)
#else #else
#define ASSEMBLE_ADD_WITH_OVERFLOW32 ASSEMBLE_ADD_WITH_OVERFLOW #define ASSEMBLE_ADD_WITH_OVERFLOW32 ASSEMBLE_ADD_WITH_OVERFLOW
...@@ -462,7 +452,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { ...@@ -462,7 +452,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
__ asm_instr(value, operand); \ __ asm_instr(value, operand); \
} while (0) } while (0)
// TODO(mbrandy): fix paths that produce garbage in offset's upper 32-bits.
#define ASSEMBLE_CHECKED_LOAD_FLOAT(asm_instr, width) \ #define ASSEMBLE_CHECKED_LOAD_FLOAT(asm_instr, width) \
do { \ do { \
DoubleRegister result = i.OutputDoubleRegister(); \ DoubleRegister result = i.OutputDoubleRegister(); \
...@@ -470,7 +459,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { ...@@ -470,7 +459,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
AddressingMode mode = kMode_None; \ AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode, index); \ MemOperand operand = i.MemoryOperand(&mode, index); \
Register offset = operand.rb(); \ Register offset = operand.rb(); \
__ lgfr(offset, offset); \
if (HasRegisterInput(instr, 2)) { \ if (HasRegisterInput(instr, 2)) { \
__ CmpLogical32(offset, i.InputRegister(2)); \ __ CmpLogical32(offset, i.InputRegister(2)); \
} else { \ } else { \
...@@ -482,7 +470,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { ...@@ -482,7 +470,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
__ bind(ool->exit()); \ __ bind(ool->exit()); \
} while (0) } while (0)
// TODO(mbrandy): fix paths that produce garbage in offset's upper 32-bits.
#define ASSEMBLE_CHECKED_LOAD_INTEGER(asm_instr) \ #define ASSEMBLE_CHECKED_LOAD_INTEGER(asm_instr) \
do { \ do { \
Register result = i.OutputRegister(); \ Register result = i.OutputRegister(); \
...@@ -490,7 +477,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { ...@@ -490,7 +477,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
AddressingMode mode = kMode_None; \ AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode, index); \ MemOperand operand = i.MemoryOperand(&mode, index); \
Register offset = operand.rb(); \ Register offset = operand.rb(); \
__ lgfr(offset, offset); \
if (HasRegisterInput(instr, 2)) { \ if (HasRegisterInput(instr, 2)) { \
__ CmpLogical32(offset, i.InputRegister(2)); \ __ CmpLogical32(offset, i.InputRegister(2)); \
} else { \ } else { \
...@@ -502,7 +488,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { ...@@ -502,7 +488,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
__ bind(ool->exit()); \ __ bind(ool->exit()); \
} while (0) } while (0)
// TODO(mbrandy): fix paths that produce garbage in offset's upper 32-bits.
#define ASSEMBLE_CHECKED_STORE_FLOAT32() \ #define ASSEMBLE_CHECKED_STORE_FLOAT32() \
do { \ do { \
Label done; \ Label done; \
...@@ -510,7 +495,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { ...@@ -510,7 +495,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
AddressingMode mode = kMode_None; \ AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode, index); \ MemOperand operand = i.MemoryOperand(&mode, index); \
Register offset = operand.rb(); \ Register offset = operand.rb(); \
__ lgfr(offset, offset); \
if (HasRegisterInput(instr, 2)) { \ if (HasRegisterInput(instr, 2)) { \
__ CmpLogical32(offset, i.InputRegister(2)); \ __ CmpLogical32(offset, i.InputRegister(2)); \
} else { \ } else { \
...@@ -522,7 +506,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { ...@@ -522,7 +506,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
__ bind(&done); \ __ bind(&done); \
} while (0) } while (0)
// TODO(mbrandy): fix paths that produce garbage in offset's upper 32-bits.
#define ASSEMBLE_CHECKED_STORE_DOUBLE() \ #define ASSEMBLE_CHECKED_STORE_DOUBLE() \
do { \ do { \
Label done; \ Label done; \
...@@ -531,7 +514,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { ...@@ -531,7 +514,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
MemOperand operand = i.MemoryOperand(&mode, index); \ MemOperand operand = i.MemoryOperand(&mode, index); \
DCHECK_EQ(kMode_MRR, mode); \ DCHECK_EQ(kMode_MRR, mode); \
Register offset = operand.rb(); \ Register offset = operand.rb(); \
__ lgfr(offset, offset); \
if (HasRegisterInput(instr, 2)) { \ if (HasRegisterInput(instr, 2)) { \
__ CmpLogical32(offset, i.InputRegister(2)); \ __ CmpLogical32(offset, i.InputRegister(2)); \
} else { \ } else { \
...@@ -543,7 +525,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { ...@@ -543,7 +525,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
__ bind(&done); \ __ bind(&done); \
} while (0) } while (0)
// TODO(mbrandy): fix paths that produce garbage in offset's upper 32-bits.
#define ASSEMBLE_CHECKED_STORE_INTEGER(asm_instr) \ #define ASSEMBLE_CHECKED_STORE_INTEGER(asm_instr) \
do { \ do { \
Label done; \ Label done; \
...@@ -551,7 +532,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { ...@@ -551,7 +532,6 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
AddressingMode mode = kMode_None; \ AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode, index); \ MemOperand operand = i.MemoryOperand(&mode, index); \
Register offset = operand.rb(); \ Register offset = operand.rb(); \
__ lgfr(offset, offset); \
if (HasRegisterInput(instr, 2)) { \ if (HasRegisterInput(instr, 2)) { \
__ CmpLogical32(offset, i.InputRegister(2)); \ __ CmpLogical32(offset, i.InputRegister(2)); \
} else { \ } else { \
...@@ -1570,6 +1550,9 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) { ...@@ -1570,6 +1550,9 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
case kS390_LoadWordS16: case kS390_LoadWordS16:
ASSEMBLE_LOAD_INTEGER(LoadHalfWordP); ASSEMBLE_LOAD_INTEGER(LoadHalfWordP);
break; break;
case kS390_LoadWordU32:
ASSEMBLE_LOAD_INTEGER(LoadlW);
break;
case kS390_LoadWordS32: case kS390_LoadWordS32:
ASSEMBLE_LOAD_INTEGER(LoadW); ASSEMBLE_LOAD_INTEGER(LoadW);
break; break;
...@@ -1622,7 +1605,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) { ...@@ -1622,7 +1605,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
ASSEMBLE_CHECKED_LOAD_INTEGER(LoadLogicalHalfWordP); ASSEMBLE_CHECKED_LOAD_INTEGER(LoadLogicalHalfWordP);
break; break;
case kCheckedLoadWord32: case kCheckedLoadWord32:
ASSEMBLE_CHECKED_LOAD_INTEGER(LoadW); ASSEMBLE_CHECKED_LOAD_INTEGER(LoadlW);
break; break;
case kCheckedLoadWord64: case kCheckedLoadWord64:
#if V8_TARGET_ARCH_S390X #if V8_TARGET_ARCH_S390X
...@@ -1672,7 +1655,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) { ...@@ -1672,7 +1655,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ LoadLogicalHalfWordP(i.OutputRegister(), i.MemoryOperand()); __ LoadLogicalHalfWordP(i.OutputRegister(), i.MemoryOperand());
break; break;
case kAtomicLoadWord32: case kAtomicLoadWord32:
__ Load(i.OutputRegister(), i.MemoryOperand()); __ LoadlW(i.OutputRegister(), i.MemoryOperand());
break; break;
default: default:
UNREACHABLE(); UNREACHABLE();
...@@ -1774,7 +1757,7 @@ void CodeGenerator::AssembleArchLookupSwitch(Instruction* instr) { ...@@ -1774,7 +1757,7 @@ void CodeGenerator::AssembleArchLookupSwitch(Instruction* instr) {
S390OperandConverter i(this, instr); S390OperandConverter i(this, instr);
Register input = i.InputRegister(0); Register input = i.InputRegister(0);
for (size_t index = 2; index < instr->InputCount(); index += 2) { for (size_t index = 2; index < instr->InputCount(); index += 2) {
__ CmpP(input, Operand(i.InputInt32(index + 0))); __ Cmp32(input, Operand(i.InputInt32(index + 0)));
__ beq(GetLabel(i.InputRpo(index + 1))); __ beq(GetLabel(i.InputRpo(index + 1)));
} }
AssembleArchJump(i.InputRpo(1)); AssembleArchJump(i.InputRpo(1));
......
src/compiler/s390/instruction-codes-s390.h
View file @ 6382a610
...@@ -126,6 +126,7 @@ namespace compiler { ...@@ -126,6 +126,7 @@ namespace compiler {
V(S390_LoadWordS16) \ V(S390_LoadWordS16) \
V(S390_LoadWordU16) \ V(S390_LoadWordU16) \
V(S390_LoadWordS32) \ V(S390_LoadWordS32) \
V(S390_LoadWordU32) \
V(S390_LoadWord64) \ V(S390_LoadWord64) \
V(S390_LoadFloat32) \ V(S390_LoadFloat32) \
V(S390_LoadDouble) \ V(S390_LoadDouble) \
......
src/compiler/s390/instruction-scheduler-s390.cc
View file @ 6382a610
...@@ -126,6 +126,7 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -126,6 +126,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_LoadWordS16: case kS390_LoadWordS16:
case kS390_LoadWordU16: case kS390_LoadWordU16:
case kS390_LoadWordS32: case kS390_LoadWordS32:
case kS390_LoadWordU32:
case kS390_LoadWord64: case kS390_LoadWord64:
case kS390_LoadFloat32: case kS390_LoadFloat32:
case kS390_LoadDouble: case kS390_LoadDouble:
......
src/compiler/s390/instruction-selector-s390.cc
View file @ 6382a610
...@@ -182,11 +182,7 @@ void InstructionSelector::VisitLoad(Node* node) { ...@@ -182,11 +182,7 @@ void InstructionSelector::VisitLoad(Node* node) {
case MachineRepresentation::kTagged: // Fall through. case MachineRepresentation::kTagged: // Fall through.
#endif #endif
case MachineRepresentation::kWord32: case MachineRepresentation::kWord32:
opcode = kS390_LoadWordS32; opcode = kS390_LoadWordU32;
#if V8_TARGET_ARCH_S390X
// TODO(john.yan): Remove this mode since s390 do not has this restriction
mode = kInt16Imm_4ByteAligned;
#endif
break; break;
#if V8_TARGET_ARCH_S390X #if V8_TARGET_ARCH_S390X
case MachineRepresentation::kTagged: // Fall through. case MachineRepresentation::kTagged: // Fall through.
......
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