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Commit 635eea88 authored by gdeepti's avatar gdeepti Committed by Commit bot
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[wasm] Implement first set of SIMD I8x16 ops 

 - I8x16Splat, I8x16ExtractLane, I8x16ReplaceLane
 - Binops: I8x16Add, I8x16AddSaturateS, I8x16Sub, I8x16SubSaturateS, I8x16MinS,
 I8x16MaxS, I8x16AddSaturateU, I8x16SubSaturateU, I8x16MinU, I8x16MaxU
 - Compare ops: I8x16Eq, I8x16Ne

BUG=v8:6020

R=bbudge@chromium.org, bmeurer@chromium.org

Review-Url: https://codereview.chromium.org/2829483002
Cr-Commit-Position: refs/heads/master@{#44706}
parent 64c12860
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Showing with 151 additions and 14 deletions
src/compiler/instruction-selector.cc
View file @ 635eea88
...@@ -2287,13 +2287,17 @@ void InstructionSelector::VisitI16x8UConvertI32x4(Node* node) { ...@@ -2287,13 +2287,17 @@ void InstructionSelector::VisitI16x8UConvertI32x4(Node* node) {
void InstructionSelector::VisitI16x8LtU(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI16x8LtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8LeU(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI16x8LeU(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitI8x16Splat(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16Splat(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16ExtractLane(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16ExtractLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16ReplaceLane(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16ReplaceLane(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitI8x16Neg(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16Shl(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16Shl(Node* node) { UNIMPLEMENTED(); }
...@@ -2303,7 +2307,9 @@ void InstructionSelector::VisitI8x16ShrS(Node* node) { UNIMPLEMENTED(); } ...@@ -2303,7 +2307,9 @@ void InstructionSelector::VisitI8x16ShrS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16SConvertI16x8(Node* node) { void InstructionSelector::VisitI8x16SConvertI16x8(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
#endif // !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitI8x16Add(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16Add(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16AddSaturateS(Node* node) { void InstructionSelector::VisitI8x16AddSaturateS(Node* node) {
...@@ -2316,8 +2322,6 @@ void InstructionSelector::VisitI8x16SubSaturateS(Node* node) { ...@@ -2316,8 +2322,6 @@ void InstructionSelector::VisitI8x16SubSaturateS(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
void InstructionSelector::VisitI8x16Mul(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16MinS(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16MinS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16MaxS(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16MaxS(Node* node) { UNIMPLEMENTED(); }
...@@ -2325,6 +2329,10 @@ void InstructionSelector::VisitI8x16MaxS(Node* node) { UNIMPLEMENTED(); } ...@@ -2325,6 +2329,10 @@ void InstructionSelector::VisitI8x16MaxS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16Eq(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16Eq(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16Ne(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16Ne(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitI8x16Mul(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16LtS(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16LtS(Node* node) { UNIMPLEMENTED(); }
...@@ -2335,7 +2343,9 @@ void InstructionSelector::VisitI8x16ShrU(Node* node) { UNIMPLEMENTED(); } ...@@ -2335,7 +2343,9 @@ void InstructionSelector::VisitI8x16ShrU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16UConvertI16x8(Node* node) { void InstructionSelector::VisitI8x16UConvertI16x8(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
#endif // !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitI8x16AddSaturateU(Node* node) { void InstructionSelector::VisitI8x16AddSaturateU(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
...@@ -2347,7 +2357,9 @@ void InstructionSelector::VisitI8x16SubSaturateU(Node* node) { ...@@ -2347,7 +2357,9 @@ void InstructionSelector::VisitI8x16SubSaturateU(Node* node) {
void InstructionSelector::VisitI8x16MinU(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16MinU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16MaxU(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16MaxU(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitI8x16LtU(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16LtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16LeU(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16LeU(Node* node) { UNIMPLEMENTED(); }
...@@ -2381,11 +2393,11 @@ void InstructionSelector::VisitS32x4Select(Node* node) { UNIMPLEMENTED(); } ...@@ -2381,11 +2393,11 @@ void InstructionSelector::VisitS32x4Select(Node* node) { UNIMPLEMENTED(); }
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitS16x8Select(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitS16x8Select(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitS8x16Select(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitS8x16Select(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitS1x4And(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitS1x4And(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x4Or(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitS1x4Or(Node* node) { UNIMPLEMENTED(); }
......
src/compiler/x64/code-generator-x64.cc
View file @ 635eea88
...@@ -2331,6 +2331,85 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2331,6 +2331,85 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ pmaxuw(i.OutputSimd128Register(), i.InputSimd128Register(1)); __ pmaxuw(i.OutputSimd128Register(), i.InputSimd128Register(1));
break; break;
} }
case kX64I8x16Splat: {
CpuFeatureScope sse_scope(masm(), SSSE3);
XMMRegister dst = i.OutputSimd128Register();
__ movd(dst, i.InputRegister(0));
__ xorps(kScratchDoubleReg, kScratchDoubleReg);
__ pshufb(dst, kScratchDoubleReg);
break;
}
case kX64I8x16ExtractLane: {
CpuFeatureScope sse_scope(masm(), SSE4_1);
Register dst = i.OutputRegister();
__ pextrb(dst, i.InputSimd128Register(0), i.InputInt8(1));
__ movsxbl(dst, dst);
break;
}
case kX64I8x16ReplaceLane: {
CpuFeatureScope sse_scope(masm(), SSE4_1);
if (instr->InputAt(2)->IsRegister()) {
__ pinsrb(i.OutputSimd128Register(), i.InputRegister(2),
i.InputInt8(1));
} else {
__ pinsrb(i.OutputSimd128Register(), i.InputOperand(2), i.InputInt8(1));
}
break;
}
case kX64I8x16Add: {
__ paddb(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I8x16AddSaturateS: {
__ paddsb(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I8x16Sub: {
__ psubb(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I8x16SubSaturateS: {
__ psubsb(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I8x16MinS: {
CpuFeatureScope sse_scope(masm(), SSE4_1);
__ pminsb(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I8x16MaxS: {
CpuFeatureScope sse_scope(masm(), SSE4_1);
__ pmaxsb(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I8x16Eq: {
__ pcmpeqb(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I8x16Ne: {
__ pcmpeqb(i.OutputSimd128Register(), i.InputSimd128Register(1));
__ pcmpeqb(kScratchDoubleReg, kScratchDoubleReg);
__ pxor(i.OutputSimd128Register(), kScratchDoubleReg);
break;
}
case kX64I8x16AddSaturateU: {
__ paddusb(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I8x16SubSaturateU: {
__ psubusb(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I8x16MinU: {
CpuFeatureScope sse_scope(masm(), SSE4_1);
__ pminub(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I8x16MaxU: {
CpuFeatureScope sse_scope(masm(), SSE4_1);
__ pmaxub(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64S128Select: { case kX64S128Select: {
// Mask used here is stored in dst. // Mask used here is stored in dst.
XMMRegister dst = i.OutputSimd128Register(); XMMRegister dst = i.OutputSimd128Register();
......
src/compiler/x64/instruction-codes-x64.h
View file @ 635eea88
...@@ -177,6 +177,21 @@ namespace compiler { ...@@ -177,6 +177,21 @@ namespace compiler {
V(X64I16x8SubSaturateU) \ V(X64I16x8SubSaturateU) \
V(X64I16x8MinU) \ V(X64I16x8MinU) \
V(X64I16x8MaxU) \ V(X64I16x8MaxU) \
V(X64I8x16Splat) \
V(X64I8x16ExtractLane) \
V(X64I8x16ReplaceLane) \
V(X64I8x16Add) \
V(X64I8x16AddSaturateS) \
V(X64I8x16Sub) \
V(X64I8x16SubSaturateS) \
V(X64I8x16MinS) \
V(X64I8x16MaxS) \
V(X64I8x16Eq) \
V(X64I8x16Ne) \
V(X64I8x16AddSaturateU) \
V(X64I8x16SubSaturateU) \
V(X64I8x16MinU) \
V(X64I8x16MaxU) \
V(X64S128Select) \ V(X64S128Select) \
V(X64S128Zero) V(X64S128Zero)
......
src/compiler/x64/instruction-scheduler-x64.cc
View file @ 635eea88
...@@ -157,6 +157,21 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -157,6 +157,21 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kX64I16x8SubSaturateU: case kX64I16x8SubSaturateU:
case kX64I16x8MinU: case kX64I16x8MinU:
case kX64I16x8MaxU: case kX64I16x8MaxU:
case kX64I8x16Splat:
case kX64I8x16ExtractLane:
case kX64I8x16ReplaceLane:
case kX64I8x16Add:
case kX64I8x16AddSaturateS:
case kX64I8x16Sub:
case kX64I8x16SubSaturateS:
case kX64I8x16MinS:
case kX64I8x16MaxS:
case kX64I8x16Eq:
case kX64I8x16Ne:
case kX64I8x16AddSaturateU:
case kX64I8x16SubSaturateU:
case kX64I8x16MinU:
case kX64I8x16MaxU:
case kX64S128Select: case kX64S128Select:
case kX64S128Zero: case kX64S128Zero:
return (instr->addressing_mode() == kMode_None) return (instr->addressing_mode() == kMode_None)
......
src/compiler/x64/instruction-selector-x64.cc
View file @ 635eea88
...@@ -2440,11 +2440,13 @@ VISIT_ATOMIC_BINOP(Xor) ...@@ -2440,11 +2440,13 @@ VISIT_ATOMIC_BINOP(Xor)
#define SIMD_TYPES(V) \ #define SIMD_TYPES(V) \
V(I32x4) \ V(I32x4) \
V(I16x8) V(I16x8) \
V(I8x16)
#define SIMD_FORMAT_LIST(V) \ #define SIMD_FORMAT_LIST(V) \
V(32x4) \ V(32x4) \
V(16x8) V(16x8) \
V(8x16)
#define SIMD_ZERO_OP_LIST(V) \ #define SIMD_ZERO_OP_LIST(V) \
V(S128Zero) \ V(S128Zero) \
...@@ -2474,7 +2476,19 @@ VISIT_ATOMIC_BINOP(Xor) ...@@ -2474,7 +2476,19 @@ VISIT_ATOMIC_BINOP(Xor)
V(I16x8AddSaturateU) \ V(I16x8AddSaturateU) \
V(I16x8SubSaturateU) \ V(I16x8SubSaturateU) \
V(I16x8MinU) \ V(I16x8MinU) \
V(I16x8MaxU) V(I16x8MaxU) \
V(I8x16Add) \
V(I8x16AddSaturateS) \
V(I8x16Sub) \
V(I8x16SubSaturateS) \
V(I8x16MinS) \
V(I8x16MaxS) \
V(I8x16Eq) \
V(I8x16Ne) \
V(I8x16AddSaturateU) \
V(I8x16SubSaturateU) \
V(I8x16MinU) \
V(I8x16MaxU)
#define SIMD_SHIFT_OPCODES(V) \ #define SIMD_SHIFT_OPCODES(V) \
V(I32x4Shl) \ V(I32x4Shl) \
......
test/cctest/wasm/test-run-wasm-simd.cc
View file @ 635eea88
...@@ -749,9 +749,7 @@ WASM_EXEC_COMPILED_TEST(I16x8ReplaceLane) { ...@@ -749,9 +749,7 @@ WASM_EXEC_COMPILED_TEST(I16x8ReplaceLane) {
CHECK_EQ(1, r.Call(1, 2)); CHECK_EQ(1, r.Call(1, 2));
} }
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64
#if V8_TARGET_ARCH_ARM
WASM_EXEC_COMPILED_TEST(I8x16Splat) { WASM_EXEC_COMPILED_TEST(I8x16Splat) {
FLAG_wasm_simd_prototype = true; FLAG_wasm_simd_prototype = true;
...@@ -869,7 +867,7 @@ WASM_EXEC_COMPILED_TEST(I8x16ReplaceLane) { ...@@ -869,7 +867,7 @@ WASM_EXEC_COMPILED_TEST(I8x16ReplaceLane) {
CHECK_EQ(1, r.Call(1, 2)); CHECK_EQ(1, r.Call(1, 2));
} }
#endif // V8_TARGET_ARCH_ARM #endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64
#if V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET || V8_TARGET_ARCH_MIPS || \ #if V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64 V8_TARGET_ARCH_MIPS64
...@@ -1400,7 +1398,9 @@ WASM_EXEC_COMPILED_TEST(I8x16ConvertI16x8) { ...@@ -1400,7 +1398,9 @@ WASM_EXEC_COMPILED_TEST(I8x16ConvertI16x8) {
CHECK_EQ(1, r.Call(*i, packed_signed, packed_unsigned)); CHECK_EQ(1, r.Call(*i, packed_signed, packed_unsigned));
} }
} }
#endif // V8_TARGET_ARCH_ARM
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64
void RunI8x16BinOpTest(WasmOpcode simd_op, Int8BinOp expected_op) { void RunI8x16BinOpTest(WasmOpcode simd_op, Int8BinOp expected_op) {
FLAG_wasm_simd_prototype = true; FLAG_wasm_simd_prototype = true;
WasmRunner<int32_t, int32_t, int32_t, int32_t> r(kExecuteCompiled); WasmRunner<int32_t, int32_t, int32_t, int32_t> r(kExecuteCompiled);
...@@ -1432,8 +1432,6 @@ WASM_EXEC_COMPILED_TEST(I8x16SubSaturateS) { ...@@ -1432,8 +1432,6 @@ WASM_EXEC_COMPILED_TEST(I8x16SubSaturateS) {
RunI8x16BinOpTest(kExprI8x16SubSaturateS, SubSaturate); RunI8x16BinOpTest(kExprI8x16SubSaturateS, SubSaturate);
} }
WASM_EXEC_COMPILED_TEST(I8x16Mul) { RunI8x16BinOpTest(kExprI8x16Mul, Mul); }
WASM_EXEC_COMPILED_TEST(I8x16MinS) { WASM_EXEC_COMPILED_TEST(I8x16MinS) {
RunI8x16BinOpTest(kExprI8x16MinS, Minimum); RunI8x16BinOpTest(kExprI8x16MinS, Minimum);
} }
...@@ -1484,6 +1482,10 @@ WASM_EXEC_COMPILED_TEST(I8x16Eq) { RunI8x16CompareOpTest(kExprI8x16Eq, Equal); } ...@@ -1484,6 +1482,10 @@ WASM_EXEC_COMPILED_TEST(I8x16Eq) { RunI8x16CompareOpTest(kExprI8x16Eq, Equal); }
WASM_EXEC_COMPILED_TEST(I8x16Ne) { WASM_EXEC_COMPILED_TEST(I8x16Ne) {
RunI8x16CompareOpTest(kExprI8x16Ne, NotEqual); RunI8x16CompareOpTest(kExprI8x16Ne, NotEqual);
} }
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64
#if V8_TARGET_ARCH_ARM
WASM_EXEC_COMPILED_TEST(I8x16Mul) { RunI8x16BinOpTest(kExprI8x16Mul, Mul); }
WASM_EXEC_COMPILED_TEST(I8x16GtS) { WASM_EXEC_COMPILED_TEST(I8x16GtS) {
RunI8x16CompareOpTest(kExprI8x16GtS, Greater); RunI8x16CompareOpTest(kExprI8x16GtS, Greater);
...@@ -1588,11 +1590,11 @@ WASM_SIMD_SELECT_TEST(32x4) ...@@ -1588,11 +1590,11 @@ WASM_SIMD_SELECT_TEST(32x4)
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 #if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64
WASM_SIMD_SELECT_TEST(16x8) WASM_SIMD_SELECT_TEST(16x8)
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64
#if V8_TARGET_ARCH_ARM
WASM_SIMD_SELECT_TEST(8x16) WASM_SIMD_SELECT_TEST(8x16)
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64
#if V8_TARGET_ARCH_ARM
// Boolean unary operations are 'AllTrue' and 'AnyTrue', which return an integer // Boolean unary operations are 'AllTrue' and 'AnyTrue', which return an integer
// result. Use relational ops on numeric vectors to create the boolean vector // result. Use relational ops on numeric vectors to create the boolean vector
// test inputs. Test inputs with all true, all false, one true, and one false. // test inputs. Test inputs with all true, all false, one true, and one false.
......
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