[wasm-simd] Guard i64x2 widen i32x4 behind post-mvp flag

These are still not in proposal, so they should be behind the post-mvp
flag.

Bug: v8:10972
Change-Id: I1b53307f334ddd8e21a095c13d7f7abb8ce05203
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2465654
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70463}

src/wasm/wasm-opcodes.h

@@ -417,10 +417,6 @@ bool V8_EXPORT_PRIVATE IsJSCompatibleSignature(const FunctionSig* sig,
   V(I32x4MaxS, 0xfdb8, s_ss)                 \
   V(I32x4MaxU, 0xfdb9, s_ss)                 \
   V(I64x2Neg, 0xfdc1, s_s)                   \
-  V(I64x2SConvertI32x4Low, 0xfdc7, s_s)      \
-  V(I64x2SConvertI32x4High, 0xfdc8, s_s)     \
-  V(I64x2UConvertI32x4Low, 0xfdc9, s_s)      \
-  V(I64x2UConvertI32x4High, 0xfdca, s_s)     \
   V(I64x2Shl, 0xfdcb, s_si)                  \
   V(I64x2ShrS, 0xfdcc, s_si)                 \
   V(I64x2ShrU, 0xfdcd, s_si)                 \
@@ -470,21 +466,25 @@ bool V8_EXPORT_PRIVATE IsJSCompatibleSignature(const FunctionSig* sig,
   V(S128Load32Lane, 0xfd5a, s_is)           \
   V(S128Load64Lane, 0xfd5b, s_is)
 
-#define FOREACH_SIMD_POST_MVP_OPCODE(V) \
-  V(I8x16Mul, 0xfd75, s_ss)             \
-  V(I8x16Popcnt, 0xfd7c, s_s)           \
-  V(I16x8Q15MulRSatS, 0xfd9c, s_ss)     \
-  V(I64x2Eq, 0xfdc0, s_ss)              \
-  V(F32x4Qfma, 0xfdb4, s_sss)           \
-  V(I64x2BitMask, 0xfdc4, i_s)          \
-  V(F32x4Qfms, 0xfdd4, s_sss)           \
-  V(F64x2Qfma, 0xfdfe, s_sss)           \
-  V(F64x2Qfms, 0xfdff, s_sss)           \
-  V(I16x8AddHoriz, 0xfdaf, s_ss)        \
-  V(I32x4AddHoriz, 0xfdb0, s_ss)        \
-  V(I32x4DotI16x8S, 0xfdba, s_ss)       \
-  V(F32x4AddHoriz, 0xfdb2, s_ss)        \
-  V(F32x4RecipApprox, 0xfdb3, s_s)      \
+#define FOREACH_SIMD_POST_MVP_OPCODE(V)  \
+  V(I8x16Mul, 0xfd75, s_ss)              \
+  V(I8x16Popcnt, 0xfd7c, s_s)            \
+  V(I16x8Q15MulRSatS, 0xfd9c, s_ss)      \
+  V(I64x2Eq, 0xfdc0, s_ss)               \
+  V(F32x4Qfma, 0xfdb4, s_sss)            \
+  V(I64x2BitMask, 0xfdc4, i_s)           \
+  V(I64x2SConvertI32x4Low, 0xfdc7, s_s)  \
+  V(I64x2SConvertI32x4High, 0xfdc8, s_s) \
+  V(I64x2UConvertI32x4Low, 0xfdc9, s_s)  \
+  V(I64x2UConvertI32x4High, 0xfdca, s_s) \
+  V(F32x4Qfms, 0xfdd4, s_sss)            \
+  V(F64x2Qfma, 0xfdfe, s_sss)            \
+  V(F64x2Qfms, 0xfdff, s_sss)            \
+  V(I16x8AddHoriz, 0xfdaf, s_ss)         \
+  V(I32x4AddHoriz, 0xfdb0, s_ss)         \
+  V(I32x4DotI16x8S, 0xfdba, s_ss)        \
+  V(F32x4AddHoriz, 0xfdb2, s_ss)         \
+  V(F32x4RecipApprox, 0xfdb3, s_s)       \
   V(F32x4RecipSqrtApprox, 0xfdbc, s_s)
 
 #define FOREACH_SIMD_1_OPERAND_1_PARAM_OPCODE(V) \

test/cctest/wasm/test-run-wasm-simd.cc

@@ -1758,6 +1758,7 @@ WASM_SIMD_TEST(I32x4ConvertI16x8) {
 // Tests both signed and unsigned conversion from I32x4 (unpacking).
 #if V8_TARGET_ARCH_ARM64
 WASM_SIMD_TEST_NO_LOWERING(I64x2ConvertI32x4) {
+  FLAG_SCOPE(wasm_simd_post_mvp);
   WasmRunner<int32_t, int32_t> r(execution_tier, lower_simd);
   // Create four output vectors to hold signed and unsigned results.
   int64_t* g0 = r.builder().AddGlobal<int64_t>(kWasmS128);