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Commit 61588f73 authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ
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S390 [liftoff]: Implement simd128 bitwise ops 

Implementations are added to macro-assembler to be shared between
liftoff and code generator.

Change-Id: Ia26b82de3f0af076ace3d53e285917029d2d5ac4
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3407794Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#78746}
parent 0e07eb53
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Showing with 30 additions and 66 deletions
src/codegen/s390/macro-assembler-s390.cc
View file @ 61588f73
......@@ -5224,6 +5224,10 @@ void TurboAssembler::I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
vlvg(dst, src2, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
}
void TurboAssembler::S128Not(Simd128Register dst, Simd128Register src) {
vno(dst, src, src, Condition(0), Condition(0), Condition(0));
}
#define SIMD_UNOP_LIST_VRR_A(V) \
V(F64x2Abs, vfpso, 2, 0, 3) \
V(F64x2Neg, vfpso, 0, 0, 3) \
......@@ -5314,7 +5318,11 @@ SIMD_BINOP_LIST_VRR_B(EMIT_SIMD_BINOP_VRR_B)
V(I8x16MinS, vmn, 0, 0, 0) \
V(I8x16MinU, vmnl, 0, 0, 0) \
V(I8x16MaxS, vmx, 0, 0, 0) \
V(I8x16MaxU, vmxl, 0, 0, 0)
V(I8x16MaxU, vmxl, 0, 0, 0) \
V(S128And, vn, 0, 0, 0) \
V(S128Or, vo, 0, 0, 0) \
V(S128Xor, vx, 0, 0, 0) \
V(S128AndNot, vnc, 0, 0, 0)
#define EMIT_SIMD_BINOP_VRR_C(name, op, c1, c2, c3) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
......
src/codegen/s390/macro-assembler-s390.h
View file @ 61588f73
......@@ -1128,7 +1128,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
V(I64x2Neg) \
V(I32x4Neg) \
V(I16x8Neg) \
V(I8x16Neg)
V(I8x16Neg) \
V(S128Not)
#define PROTOTYPE_SIMD_UNOP(name) \
void name(Simd128Register dst, Simd128Register src);
......@@ -1225,7 +1226,11 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
V(I8x16ShrU, Register) \
V(I8x16Shl, const Operand&) \
V(I8x16ShrS, const Operand&) \
V(I8x16ShrU, const Operand&)
V(I8x16ShrU, const Operand&) \
V(S128And, Simd128Register) \
V(S128Or, Simd128Register) \
V(S128Xor, Simd128Register) \
V(S128AndNot, Simd128Register)
#define PROTOTYPE_SIMD_BINOP(name, stype) \
void name(Simd128Register dst, Simd128Register src1, stype src2);
......
src/compiler/backend/s390/code-generator-s390.cc
View file @ 61588f73
......@@ -2631,7 +2631,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
V(I8x16MaxU, Simd128Register) \
V(I8x16Shl, Register) \
V(I8x16ShrS, Register) \
V(I8x16ShrU, Register)
V(I8x16ShrU, Register) \
V(S128And, Simd128Register) \
V(S128Or, Simd128Register) \
V(S128Xor, Simd128Register) \
V(S128AndNot, Simd128Register)
#define EMIT_SIMD_BINOP(name, stype) \
case kS390_##name: { \
......@@ -2671,7 +2675,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
V(I64x2Neg, Simd128Register, Simd128Register) \
V(I32x4Neg, Simd128Register, Simd128Register) \
V(I16x8Neg, Simd128Register, Simd128Register) \
V(I8x16Neg, Simd128Register, Simd128Register)
V(I8x16Neg, Simd128Register, Simd128Register) \
V(S128Not, Simd128Register, Simd128Register)
#define EMIT_SIMD_UNOP(name, dtype, stype) \
case kS390_##name: { \
......@@ -2784,12 +2789,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(2));
break;
}
case kS390_S128Not: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
__ vno(dst, src, src, Condition(0), Condition(0), Condition(0));
break;
}
// vector boolean unops
case kS390_V128AnyTrue: {
Simd128Register src = i.InputSimd128Register(0);
......@@ -2830,27 +2829,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
#undef SIMD_ALL_TRUE
// vector bitwise ops
case kS390_S128And: {
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src = i.InputSimd128Register(1);
__ vn(dst, i.InputSimd128Register(0), src, Condition(0), Condition(0),
Condition(0));
break;
}
case kS390_S128Or: {
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src = i.InputSimd128Register(1);
__ vo(dst, i.InputSimd128Register(0), src, Condition(0), Condition(0),
Condition(0));
break;
}
case kS390_S128Xor: {
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src = i.InputSimd128Register(1);
__ vx(dst, i.InputSimd128Register(0), src, Condition(0), Condition(0),
Condition(0));
break;
}
case kS390_S128Const: {
uint64_t low = make_uint64(i.InputUint32(1), i.InputUint32(0));
uint64_t high = make_uint64(i.InputUint32(3), i.InputUint32(2));
......@@ -2877,13 +2855,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vsel(dst, src1, src2, mask, Condition(0), Condition(0));
break;
}
case kS390_S128AndNot: {
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src = i.InputSimd128Register(1);
__ vnc(dst, i.InputSimd128Register(0), src, Condition(0), Condition(0),
Condition(0));
break;
}
// vector conversions
#define CONVERT_FLOAT_TO_INT32(convert) \
for (int index = 0; index < 4; index++) { \
......
src/wasm/baseline/s390/liftoff-assembler-s390.h
View file @ 61588f73
......@@ -2342,7 +2342,11 @@ void LiftoffAssembler::emit_smi_check(Register obj, Label* target,
V(i8x16_max_u, I8x16MaxU, fp) \
V(i8x16_shl, I8x16Shl, gp) \
V(i8x16_shr_s, I8x16ShrS, gp) \
V(i8x16_shr_u, I8x16ShrU, gp)
V(i8x16_shr_u, I8x16ShrU, gp) \
V(s128_and, S128And, fp) \
V(s128_or, S128Or, fp) \
V(s128_xor, S128Xor, fp) \
V(s128_and_not, S128AndNot, fp)
#define EMIT_SIMD_BINOP_RR(name, op, stype) \
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
......@@ -2404,7 +2408,8 @@ SIMD_BINOP_RI_LIST(EMIT_SIMD_BINOP_RI)
V(i64x2_neg, I64x2Neg, fp, fp, , void) \
V(i32x4_neg, I32x4Neg, fp, fp, , void) \
V(i16x8_neg, I16x8Neg, fp, fp, , void) \
V(i8x16_neg, I8x16Neg, fp, fp, , void)
V(i8x16_neg, I8x16Neg, fp, fp, , void) \
V(s128_not, S128Not, fp, fp, , void)
#define EMIT_SIMD_UNOP(name, op, dtype, stype, return_val, return_type) \
return_type LiftoffAssembler::emit_##name(LiftoffRegister dst, \
......@@ -2751,25 +2756,6 @@ void LiftoffAssembler::emit_s128_const(LiftoffRegister dst,
bailout(kUnsupportedArchitecture, "emit_s128_const");
}
void LiftoffAssembler::emit_s128_not(LiftoffRegister dst, LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_s128_not");
}
void LiftoffAssembler::emit_s128_and(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_s128_and");
}
void LiftoffAssembler::emit_s128_or(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_s128_or");
}
void LiftoffAssembler::emit_s128_xor(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_s128_xor");
}
void LiftoffAssembler::emit_s128_select(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2,
......@@ -2876,12 +2862,6 @@ void LiftoffAssembler::emit_i32x4_trunc_sat_f64x2_u_zero(LiftoffRegister dst,
bailout(kSimd, "i32x4.trunc_sat_f64x2_u_zero");
}
void LiftoffAssembler::emit_s128_and_not(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_s128_and_not");
}
void LiftoffAssembler::emit_i8x16_rounding_average_u(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
......
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