[turbofan] ARM64: Support shifted indexes in loads and stores
This patch adds support for the `Operand2_R_LSL_I` addressing mode to loads and stores. This allows merging a shift instruction into a MemoryOperand. Since the shift immediate is restricted to the log2 of the operation width, the opportunities to hit this are slim. However, Ignition's bytecode handlers hit this case all the time: kind = BYTECODE_HANDLER name = Star compiler = turbofan Instructions (size = 44) 0x23e67280 0 add x1, x19, #0x1 (1) 0x23e67284 4 ldrsb x1, [x20, x1] 0x23e67288 8 sxtw x1, w1 0x23e6728c 12 mov x2, fp 0x23e67290 16 str x0, [x2, x1, lsl #3] ^^^^^^^^^^^^^^^^^^^^^ 0x23e67294 20 add x19, x19, #0x2 (2) 0x23e67298 24 ldrb w1, [x20, x19] 0x23e6729c 28 ldr x1, [x21, x1, lsl #3] ^^^^^^^^^^^^^^^^^^^^^ 0x23e672a0 32 br x1 Additionally, I noticed the optimisation occurs once in both the `StringPrototypeCharAt` and `StringPrototypeCharCodeAt` turbofan stubs. BUG= Review-Url: https://codereview.chromium.org/1972103002 Cr-Commit-Position: refs/heads/master@{#36227}
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