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Commit 603e13e8 authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ
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S390 [liftoff]: Initiate FP binary operations 

FP Div, Min and Max are added in this CL.

Opcodes are also reordered in macros to match the
instruction selector.

Change-Id: Idd6909721b0d06d523c93873e5faff39449d937c
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3058294Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#75965}
parent 8f62c98d
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Showing with 79 additions and 121 deletions
src/codegen/s390/macro-assembler-s390.cc
View file @ 603e13e8
......@@ -5164,28 +5164,34 @@ void TurboAssembler::I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
vlvg(dst, src2, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
}
#define SIMD_BINOP_LIST(V) \
V(F64x2Add, vfa, 3) \
V(F32x4Add, vfa, 2) \
V(I64x2Add, va, 3) \
V(I32x4Add, va, 2) \
V(I16x8Add, va, 1) \
V(I8x16Add, va, 0) \
V(F64x2Sub, vfs, 3) \
V(F32x4Sub, vfs, 2) \
V(I64x2Sub, vs, 3) \
V(I32x4Sub, vs, 2) \
V(I16x8Sub, vs, 1) \
V(I8x16Sub, vs, 0) \
V(F64x2Mul, vfm, 3) \
V(F32x4Mul, vfm, 2) \
V(I32x4Mul, vml, 2) \
V(I16x8Mul, vml, 1)
#define EMIT_SIMD_BINOP(name, op, condition) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
Simd128Register src2) { \
op(dst, src1, src2, Condition(0), Condition(0), Condition(condition)); \
#define SIMD_BINOP_LIST(V) \
V(F64x2Add, vfa, 0, 0, 3) \
V(F64x2Sub, vfs, 0, 0, 3) \
V(F64x2Mul, vfm, 0, 0, 3) \
V(F64x2Div, vfd, 0, 0, 3) \
V(F64x2Min, vfmin, 1, 0, 3) \
V(F64x2Max, vfmax, 1, 0, 3) \
V(F32x4Add, vfa, 0, 0, 2) \
V(F32x4Sub, vfs, 0, 0, 2) \
V(F32x4Mul, vfm, 0, 0, 2) \
V(F32x4Div, vfd, 0, 0, 2) \
V(F32x4Min, vfmin, 1, 0, 2) \
V(F32x4Max, vfmax, 1, 0, 2) \
V(I64x2Add, va, 0, 0, 3) \
V(I64x2Sub, vs, 0, 0, 3) \
V(I32x4Add, va, 0, 0, 2) \
V(I32x4Sub, vs, 0, 0, 2) \
V(I32x4Mul, vml, 0, 0, 2) \
V(I16x8Add, va, 0, 0, 1) \
V(I16x8Sub, vs, 0, 0, 1) \
V(I16x8Mul, vml, 0, 0, 1) \
V(I8x16Add, va, 0, 0, 0) \
V(I8x16Sub, vs, 0, 0, 0)
#define EMIT_SIMD_BINOP(name, op, c1, c2, c3) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
Simd128Register src2) { \
op(dst, src1, src2, Condition(c1), Condition(c2), Condition(c3)); \
}
SIMD_BINOP_LIST(EMIT_SIMD_BINOP)
#undef EMIT_SIMD_BINOP
......
src/codegen/s390/macro-assembler-s390.h
View file @ 603e13e8
......@@ -1065,22 +1065,28 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
#define SIMD_BINOP_LIST(V) \
V(F64x2Add) \
V(F32x4Add) \
V(I64x2Add) \
V(I32x4Add) \
V(I16x8Add) \
V(I8x16Add) \
V(F64x2Sub) \
V(F32x4Sub) \
V(I64x2Sub) \
V(I32x4Sub) \
V(I16x8Sub) \
V(I8x16Sub) \
V(F64x2Mul) \
V(F64x2Div) \
V(F64x2Min) \
V(F64x2Max) \
V(F32x4Add) \
V(F32x4Sub) \
V(F32x4Mul) \
V(F32x4Div) \
V(F32x4Min) \
V(F32x4Max) \
V(I64x2Add) \
V(I64x2Sub) \
V(I64x2Mul) \
V(I32x4Add) \
V(I32x4Sub) \
V(I32x4Mul) \
V(I16x8Mul)
V(I16x8Add) \
V(I16x8Sub) \
V(I16x8Mul) \
V(I8x16Add) \
V(I8x16Sub)
#define PROTOTYPE_SIMD_BINOP(name) \
void name(Simd128Register dst, Simd128Register src1, Simd128Register src2);
......
src/compiler/backend/s390/code-generator-s390.cc
View file @ 603e13e8
......@@ -2484,22 +2484,28 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
// Simd Support.
#define SIMD_BINOP_LIST(V) \
V(F64x2Add) \
V(F32x4Add) \
V(I64x2Add) \
V(I32x4Add) \
V(I16x8Add) \
V(I8x16Add) \
V(F64x2Sub) \
V(F32x4Sub) \
V(I64x2Sub) \
V(I32x4Sub) \
V(I16x8Sub) \
V(I8x16Sub) \
V(F64x2Mul) \
V(F64x2Div) \
V(F64x2Min) \
V(F64x2Max) \
V(F32x4Add) \
V(F32x4Sub) \
V(F32x4Mul) \
V(F32x4Div) \
V(F32x4Min) \
V(F32x4Max) \
V(I64x2Add) \
V(I64x2Sub) \
V(I64x2Mul) \
V(I32x4Add) \
V(I32x4Sub) \
V(I32x4Mul) \
V(I16x8Mul)
V(I16x8Add) \
V(I16x8Sub) \
V(I16x8Mul) \
V(I8x16Add) \
V(I8x16Sub)
#define EMIT_SIMD_BINOP(name) \
case kS390_##name: { \
......@@ -2565,24 +2571,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
#undef EMIT_SIMD_REPLACE_LANE
#undef SIMD_REPLACE_LANE_LIST
// vector binops
case kS390_F64x2Div: {
__ vfd(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(3));
break;
}
case kS390_F64x2Min: {
__ vfmin(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(1), Condition(0),
Condition(3));
break;
}
case kS390_F64x2Max: {
__ vfmax(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(1), Condition(0),
Condition(3));
break;
}
case kS390_F64x2Qfma: {
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
......@@ -2599,24 +2587,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vfnms(dst, src1, src2, src0, Condition(3), Condition(0));
break;
}
case kS390_F32x4Div: {
__ vfd(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_F32x4Min: {
__ vfmin(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(1), Condition(0),
Condition(2));
break;
}
case kS390_F32x4Max: {
__ vfmax(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(1), Condition(0),
Condition(2));
break;
}
case kS390_F32x4Qfma: {
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
......
src/wasm/baseline/s390/liftoff-assembler-s390.h
View file @ 603e13e8
......@@ -2145,22 +2145,28 @@ void LiftoffAssembler::emit_smi_check(Register obj, Label* target,
#define SIMD_BINOP_LIST(V) \
V(f64x2_add, F64x2Add) \
V(f32x4_add, F32x4Add) \
V(i64x2_add, I64x2Add) \
V(i32x4_add, I32x4Add) \
V(i16x8_add, I16x8Add) \
V(i8x16_add, I8x16Add) \
V(f64x2_sub, F64x2Sub) \
V(f32x4_sub, F32x4Sub) \
V(i64x2_sub, I64x2Sub) \
V(i32x4_sub, I32x4Sub) \
V(i16x8_sub, I16x8Sub) \
V(i8x16_sub, I8x16Sub) \
V(f64x2_mul, F64x2Mul) \
V(f64x2_div, F64x2Div) \
V(f64x2_min, F64x2Min) \
V(f64x2_max, F64x2Max) \
V(f32x4_add, F32x4Add) \
V(f32x4_sub, F32x4Sub) \
V(f32x4_mul, F32x4Mul) \
V(f32x4_div, F32x4Div) \
V(f32x4_min, F32x4Min) \
V(f32x4_max, F32x4Max) \
V(i64x2_add, I64x2Add) \
V(i64x2_sub, I64x2Sub) \
V(i64x2_mul, I64x2Mul) \
V(i32x4_add, I32x4Add) \
V(i32x4_sub, I32x4Sub) \
V(i32x4_mul, I32x4Mul) \
V(i16x8_mul, I16x8Mul)
V(i16x8_add, I16x8Add) \
V(i16x8_sub, I16x8Sub) \
V(i16x8_mul, I16x8Mul) \
V(i8x16_add, I8x16Add) \
V(i8x16_sub, I8x16Sub)
#define EMIT_SIMD_BINOP(name, op) \
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
......@@ -2292,21 +2298,6 @@ bool LiftoffAssembler::emit_f64x2_nearest_int(LiftoffRegister dst,
return true;
}
void LiftoffAssembler::emit_f64x2_div(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f64x2div");
}
void LiftoffAssembler::emit_f64x2_min(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f64x2min");
}
void LiftoffAssembler::emit_f64x2_max(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f64x2max");
}
void LiftoffAssembler::emit_f64x2_pmin(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "pmin unimplemented");
......@@ -2371,21 +2362,6 @@ bool LiftoffAssembler::emit_f32x4_nearest_int(LiftoffRegister dst,
return true;
}
void LiftoffAssembler::emit_f32x4_div(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f32x4div");
}
void LiftoffAssembler::emit_f32x4_min(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f32x4min");
}
void LiftoffAssembler::emit_f32x4_max(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f32x4max");
}
void LiftoffAssembler::emit_f32x4_pmin(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "pmin unimplemented");
......
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