PPC: refactor setting cpu features

PPC features on V8 are currently only enabled by checking the cpu
type (i.e if >= powerX then set a feature as available).
This CL bypasses the feature list and simply checks if the cpu
type is >= a specific type required by certain instructions.

Specific feature checks (such as FPU) can always be added back to the
list if needed.

Change-Id: Ic7d1f1375c28da507f96f93f879859ef3dbfe512
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3048971
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Reviewed-by: Junliang Yan <junyan@redhat.com>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/master@{#75923}

src/builtins/ppc/builtins-ppc.cc

@@ -2831,7 +2831,7 @@ static void CallApiFunctionAndReturn(MacroAssembler* masm,
   __ lbz(scratch, MemOperand(scratch, 0));
   __ cmpi(scratch, Operand::Zero());
 
-  if (CpuFeatures::IsSupported(ISELECT)) {
+  if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
     __ Move(scratch, thunk_ref);
     __ isel(eq, scratch, function_address, scratch);
   } else {

src/codegen/cpu-features.h

@@ -52,13 +52,11 @@ enum CpuFeature {
   MIPS_SIMD,  // MSA instructions
 
 #elif V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64
-  FPU,
-  FPR_GPR_MOV,
-  LWSYNC,
-  ISELECT,
-  VSX,
-  MODULO,
-  SIMD,
+  PPC_6_PLUS,
+  PPC_7_PLUS,
+  PPC_8_PLUS,
+  PPC_9_PLUS,
+  PPC_10_PLUS,
 
 #elif V8_TARGET_ARCH_S390X
   FPU,

src/codegen/ppc/assembler-ppc.cc

@@ -56,7 +56,7 @@ static unsigned CpuFeaturesImpliedByCompiler() {
 
 bool CpuFeatures::SupportsWasmSimd128() {
 #if V8_ENABLE_WEBASSEMBLY
-  return CpuFeatures::IsSupported(SIMD);
+  return CpuFeatures::IsSupported(PPC_9_PLUS);
 #else
   return false;
 #endif  // V8_ENABLE_WEBASSEMBLY
@@ -69,65 +69,33 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
   // Only use statically determined features for cross compile (snapshot).
   if (cross_compile) return;
 
-// Detect whether frim instruction is supported (POWER5+)
-// For now we will just check for processors we know do not
-// support it
-#ifndef USE_SIMULATOR
-  // Probe for additional features at runtime.
+// Probe for additional features at runtime.
+#ifdef USE_SIMULATOR
+  // Simulator
+  supported_ |= (1u << PPC_10_PLUS);
+#else
   base::CPU cpu;
-  if (cpu.part() == base::CPU::kPPCPower9 ||
-      cpu.part() == base::CPU::kPPCPower10) {
-    supported_ |= (1u << MODULO);
-  }
-#if V8_TARGET_ARCH_PPC64
-  if (cpu.part() == base::CPU::kPPCPower8 ||
-      cpu.part() == base::CPU::kPPCPower9 ||
-      cpu.part() == base::CPU::kPPCPower10) {
-    supported_ |= (1u << FPR_GPR_MOV);
-  }
-  // V8 PPC Simd implementations need P9 at a minimum.
-  if (cpu.part() == base::CPU::kPPCPower9 ||
-      cpu.part() == base::CPU::kPPCPower10) {
-    supported_ |= (1u << SIMD);
-  }
-#endif
-  if (cpu.part() == base::CPU::kPPCPower6 ||
-      cpu.part() == base::CPU::kPPCPower7 ||
-      cpu.part() == base::CPU::kPPCPower8 ||
-      cpu.part() == base::CPU::kPPCPower9 ||
-      cpu.part() == base::CPU::kPPCPower10) {
-    supported_ |= (1u << LWSYNC);
-  }
-  if (cpu.part() == base::CPU::kPPCPower7 ||
-      cpu.part() == base::CPU::kPPCPower8 ||
-      cpu.part() == base::CPU::kPPCPower9 ||
-      cpu.part() == base::CPU::kPPCPower10) {
-    supported_ |= (1u << ISELECT);
-    supported_ |= (1u << VSX);
+  if (cpu.part() == base::CPU::kPPCPower10) {
+    supported_ |= (1u << PPC_10_PLUS);
+  } else if (cpu.part() == base::CPU::kPPCPower9) {
+    supported_ |= (1u << PPC_9_PLUS);
+  } else if (cpu.part() == base::CPU::kPPCPower8) {
+    supported_ |= (1u << PPC_8_PLUS);
+  } else if (cpu.part() == base::CPU::kPPCPower7) {
+    supported_ |= (1u << PPC_7_PLUS);
+  } else if (cpu.part() == base::CPU::kPPCPower6) {
+    supported_ |= (1u << PPC_6_PLUS);
   }
 #if V8_OS_LINUX
-  if (!(cpu.part() == base::CPU::kPPCG5 || cpu.part() == base::CPU::kPPCG4)) {
-    // Assume support
-    supported_ |= (1u << FPU);
-  }
   if (cpu.icache_line_size() != base::CPU::kUnknownCacheLineSize) {
     icache_line_size_ = cpu.icache_line_size();
   }
-#elif V8_OS_AIX
-  // Assume support FP support and default cache line size
-  supported_ |= (1u << FPU);
-#endif
-#else  // Simulator
-  supported_ |= (1u << FPU);
-  supported_ |= (1u << LWSYNC);
-  supported_ |= (1u << ISELECT);
-  supported_ |= (1u << VSX);
-  supported_ |= (1u << MODULO);
-  supported_ |= (1u << SIMD);
-#if V8_TARGET_ARCH_PPC64
-  supported_ |= (1u << FPR_GPR_MOV);
 #endif
 #endif
+  if (supported_ & (1u << PPC_10_PLUS)) supported_ |= (1u << PPC_9_PLUS);
+  if (supported_ & (1u << PPC_9_PLUS)) supported_ |= (1u << PPC_8_PLUS);
+  if (supported_ & (1u << PPC_8_PLUS)) supported_ |= (1u << PPC_7_PLUS);
+  if (supported_ & (1u << PPC_7_PLUS)) supported_ |= (1u << PPC_6_PLUS);
 
   // Set a static value on whether Simd is supported.
   // This variable is only used for certain archs to query SupportWasmSimd128()
@@ -149,12 +117,11 @@ void CpuFeatures::PrintTarget() {
 }
 
 void CpuFeatures::PrintFeatures() {
-  printf("FPU=%d\n", CpuFeatures::IsSupported(FPU));
-  printf("FPR_GPR_MOV=%d\n", CpuFeatures::IsSupported(FPR_GPR_MOV));
-  printf("LWSYNC=%d\n", CpuFeatures::IsSupported(LWSYNC));
-  printf("ISELECT=%d\n", CpuFeatures::IsSupported(ISELECT));
-  printf("VSX=%d\n", CpuFeatures::IsSupported(VSX));
-  printf("MODULO=%d\n", CpuFeatures::IsSupported(MODULO));
+  printf("PPC_6_PLUS=%d\n", CpuFeatures::IsSupported(PPC_6_PLUS));
+  printf("PPC_7_PLUS=%d\n", CpuFeatures::IsSupported(PPC_7_PLUS));
+  printf("PPC_8_PLUS=%d\n", CpuFeatures::IsSupported(PPC_8_PLUS));
+  printf("PPC_9_PLUS=%d\n", CpuFeatures::IsSupported(PPC_9_PLUS));
+  printf("PPC_10_PLUS=%d\n", CpuFeatures::IsSupported(PPC_10_PLUS));
 }
 
 Register ToRegister(int num) {

src/codegen/ppc/cpu-ppc.cc

@@ -8,7 +8,7 @@
 
 #include "src/codegen/cpu-features.h"
 
-#define INSTR_AND_DATA_CACHE_COHERENCY LWSYNC
+#define INSTR_AND_DATA_CACHE_COHERENCY PPC_6_PLUS
 
 namespace v8 {
 namespace internal {

src/codegen/ppc/macro-assembler-ppc.cc

@@ -2450,7 +2450,7 @@ void TurboAssembler::LoadDoubleLiteral(DoubleRegister result,
   litVal.dval = value.AsUint64();
 
 #if V8_TARGET_ARCH_PPC64
-  if (CpuFeatures::IsSupported(FPR_GPR_MOV)) {
+  if (CpuFeatures::IsSupported(PPC_8_PLUS)) {
     mov(scratch, Operand(litVal.ival));
     mtfprd(result, scratch);
     return;
@@ -2476,7 +2476,7 @@ void TurboAssembler::MovIntToDouble(DoubleRegister dst, Register src,
                                     Register scratch) {
 // sign-extend src to 64-bit
 #if V8_TARGET_ARCH_PPC64
-  if (CpuFeatures::IsSupported(FPR_GPR_MOV)) {
+  if (CpuFeatures::IsSupported(PPC_8_PLUS)) {
     mtfprwa(dst, src);
     return;
   }
@@ -2501,7 +2501,7 @@ void TurboAssembler::MovUnsignedIntToDouble(DoubleRegister dst, Register src,
                                             Register scratch) {
 // zero-extend src to 64-bit
 #if V8_TARGET_ARCH_PPC64
-  if (CpuFeatures::IsSupported(FPR_GPR_MOV)) {
+  if (CpuFeatures::IsSupported(PPC_8_PLUS)) {
     mtfprwz(dst, src);
     return;
   }
@@ -2528,7 +2528,7 @@ void TurboAssembler::MovInt64ToDouble(DoubleRegister dst,
 #endif
                                       Register src) {
 #if V8_TARGET_ARCH_PPC64
-  if (CpuFeatures::IsSupported(FPR_GPR_MOV)) {
+  if (CpuFeatures::IsSupported(PPC_8_PLUS)) {
     mtfprd(dst, src);
     return;
   }
@@ -2551,7 +2551,7 @@ void TurboAssembler::MovInt64ComponentsToDouble(DoubleRegister dst,
                                                 Register src_hi,
                                                 Register src_lo,
                                                 Register scratch) {
-  if (CpuFeatures::IsSupported(FPR_GPR_MOV)) {
+  if (CpuFeatures::IsSupported(PPC_8_PLUS)) {
     ShiftLeftU64(scratch, src_hi, Operand(32));
     rldimi(scratch, src_lo, 0, 32);
     mtfprd(dst, scratch);
@@ -2570,7 +2570,7 @@ void TurboAssembler::MovInt64ComponentsToDouble(DoubleRegister dst,
 void TurboAssembler::InsertDoubleLow(DoubleRegister dst, Register src,
                                      Register scratch) {
 #if V8_TARGET_ARCH_PPC64
-  if (CpuFeatures::IsSupported(FPR_GPR_MOV)) {
+  if (CpuFeatures::IsSupported(PPC_8_PLUS)) {
     mffprd(scratch, dst);
     rldimi(scratch, src, 0, 32);
     mtfprd(dst, scratch);
@@ -2589,7 +2589,7 @@ void TurboAssembler::InsertDoubleLow(DoubleRegister dst, Register src,
 void TurboAssembler::InsertDoubleHigh(DoubleRegister dst, Register src,
                                       Register scratch) {
 #if V8_TARGET_ARCH_PPC64
-  if (CpuFeatures::IsSupported(FPR_GPR_MOV)) {
+  if (CpuFeatures::IsSupported(PPC_8_PLUS)) {
     mffprd(scratch, dst);
     rldimi(scratch, src, 32, 0);
     mtfprd(dst, scratch);
@@ -2607,7 +2607,7 @@ void TurboAssembler::InsertDoubleHigh(DoubleRegister dst, Register src,
 
 void TurboAssembler::MovDoubleLowToInt(Register dst, DoubleRegister src) {
 #if V8_TARGET_ARCH_PPC64
-  if (CpuFeatures::IsSupported(FPR_GPR_MOV)) {
+  if (CpuFeatures::IsSupported(PPC_8_PLUS)) {
     mffprwz(dst, src);
     return;
   }
@@ -2622,7 +2622,7 @@ void TurboAssembler::MovDoubleLowToInt(Register dst, DoubleRegister src) {
 
 void TurboAssembler::MovDoubleHighToInt(Register dst, DoubleRegister src) {
 #if V8_TARGET_ARCH_PPC64
-  if (CpuFeatures::IsSupported(FPR_GPR_MOV)) {
+  if (CpuFeatures::IsSupported(PPC_8_PLUS)) {
     mffprd(dst, src);
     srdi(dst, dst, Operand(32));
     return;
@@ -2642,7 +2642,7 @@ void TurboAssembler::MovDoubleToInt64(
 #endif
     Register dst, DoubleRegister src) {
 #if V8_TARGET_ARCH_PPC64
-  if (CpuFeatures::IsSupported(FPR_GPR_MOV)) {
+  if (CpuFeatures::IsSupported(PPC_8_PLUS)) {
     mffprd(dst, src);
     return;
   }

src/compiler/backend/ppc/code-generator-ppc.cc

@@ -1487,7 +1487,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       ASSEMBLE_FLOAT_BINOP_RC(fdiv, MiscField::decode(instr->opcode()));
       break;
     case kPPC_Mod32:
-      if (CpuFeatures::IsSupported(MODULO)) {
+      if (CpuFeatures::IsSupported(PPC_9_PLUS)) {
         __ modsw(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
         ASSEMBLE_MODULO(divw, mullw);
@@ -1495,7 +1495,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
 #if V8_TARGET_ARCH_PPC64
     case kPPC_Mod64:
-      if (CpuFeatures::IsSupported(MODULO)) {
+      if (CpuFeatures::IsSupported(PPC_9_PLUS)) {
         __ modsd(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
         ASSEMBLE_MODULO(divd, mulld);
@@ -1503,7 +1503,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
 #endif
     case kPPC_ModU32:
-      if (CpuFeatures::IsSupported(MODULO)) {
+      if (CpuFeatures::IsSupported(PPC_9_PLUS)) {
         __ moduw(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
         ASSEMBLE_MODULO(divwu, mullw);
@@ -1511,7 +1511,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
 #if V8_TARGET_ARCH_PPC64
     case kPPC_ModU64:
-      if (CpuFeatures::IsSupported(MODULO)) {
+      if (CpuFeatures::IsSupported(PPC_9_PLUS)) {
         __ modud(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
         ASSEMBLE_MODULO(divdu, mulld);
@@ -1868,7 +1868,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
             cr, static_cast<CRBit>(VXCVI % CRWIDTH));
         __ mcrfs(cr, VXCVI);  // extract FPSCR field containing VXCVI into cr7
         // Handle conversion failures (such as overflow).
-        if (CpuFeatures::IsSupported(ISELECT)) {
+        if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
           if (check_conversion) {
             __ li(i.OutputRegister(1), Operand(1));
             __ isel(i.OutputRegister(1), r0, i.OutputRegister(1), crbit);
@@ -1905,7 +1905,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
         int crbit = v8::internal::Assembler::encode_crbit(
             cr, static_cast<CRBit>(VXCVI % CRWIDTH));
         __ mcrfs(cr, VXCVI);  // extract FPSCR field containing VXCVI into cr7
-        if (CpuFeatures::IsSupported(ISELECT)) {
+        if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
           __ li(i.OutputRegister(1), Operand(1));
           __ isel(i.OutputRegister(1), r0, i.OutputRegister(1), crbit);
         } else {
@@ -3885,7 +3885,7 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
     // Unnecessary for eq/lt & ne/ge since only FU bit will be set.
   }
 
-  if (CpuFeatures::IsSupported(ISELECT)) {
+  if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
     switch (cond) {
       case eq:
       case lt: