[mips][wasm-simd][liftoff] Prototype load lane and store lane

Port: 9db3cb75

Port: 22e06c7b

Change-Id: Ib42f9729220365f1803cfbc634e3f37f5209e142
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2650045
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Auto-Submit: Liu yu <liuyu@loongson.cn>
Reviewed-by: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#72351}

src/codegen/mips64/assembler-mips64.cc

@@ -37,6 +37,7 @@
 #if V8_TARGET_ARCH_MIPS64
 
 #include "src/base/cpu.h"
+#include "src/codegen/machine-type.h"
 #include "src/codegen/mips64/assembler-mips64-inl.h"
 #include "src/codegen/safepoint-table.h"
 #include "src/codegen/string-constants.h"
@@ -3989,6 +3990,26 @@ Register UseScratchRegisterScope::Acquire() {
 
 bool UseScratchRegisterScope::hasAvailable() const { return *available_ != 0; }
 
+LoadStoreLaneParams::LoadStoreLaneParams(MachineRepresentation rep,
+                                         uint8_t laneidx) {
+  switch (rep) {
+    case MachineRepresentation::kWord8:
+      *this = LoadStoreLaneParams(laneidx, MSA_B, 16);
+      break;
+    case MachineRepresentation::kWord16:
+      *this = LoadStoreLaneParams(laneidx, MSA_H, 8);
+      break;
+    case MachineRepresentation::kWord32:
+      *this = LoadStoreLaneParams(laneidx, MSA_W, 4);
+      break;
+    case MachineRepresentation::kWord64:
+      *this = LoadStoreLaneParams(laneidx, MSA_D, 2);
+      break;
+    default:
+      UNREACHABLE();
+  }
+}
+
 }  // namespace internal
 }  // namespace v8
 

src/codegen/mips64/assembler-mips64.h

@@ -36,12 +36,14 @@
 #define V8_CODEGEN_MIPS64_ASSEMBLER_MIPS64_H_
 
 #include <stdio.h>
+
 #include <memory>
 #include <set>
 
 #include "src/codegen/assembler.h"
 #include "src/codegen/external-reference.h"
 #include "src/codegen/label.h"
+#include "src/codegen/machine-type.h"
 #include "src/codegen/mips64/constants-mips64.h"
 #include "src/codegen/mips64/register-mips64.h"
 #include "src/objects/contexts.h"
@@ -1951,6 +1953,20 @@ class V8_EXPORT_PRIVATE V8_NODISCARD UseScratchRegisterScope {
   RegList old_available_;
 };
 
+// Helper struct for load lane and store lane to indicate what memory size
+// to be encoded in the opcode, and the new lane index.
+class LoadStoreLaneParams {
+ public:
+  MSASize sz;
+  uint8_t laneidx;
+
+  LoadStoreLaneParams(MachineRepresentation rep, uint8_t laneidx);
+
+ private:
+  LoadStoreLaneParams(uint8_t laneidx, MSASize sz, int lanes)
+      : sz(sz), laneidx(laneidx % lanes) {}
+};
+
 }  // namespace internal
 }  // namespace v8
 

src/codegen/mips64/macro-assembler-mips64.cc

@@ -2633,22 +2633,24 @@ void TurboAssembler::Round_s_s(FPURegister dst, FPURegister src) {
 
 void TurboAssembler::LoadLane(MSASize sz, MSARegister dst, uint8_t laneidx,
                               MemOperand src) {
+  UseScratchRegisterScope temps(this);
+  Register scratch = temps.Acquire();
   switch (sz) {
     case MSA_B:
-      Lbu(kScratchReg, src);
-      insert_b(dst, laneidx, kScratchReg);
+      Lbu(scratch, src);
+      insert_b(dst, laneidx, scratch);
       break;
     case MSA_H:
-      Lhu(kScratchReg, src);
-      insert_h(dst, laneidx, kScratchReg);
+      Lhu(scratch, src);
+      insert_h(dst, laneidx, scratch);
       break;
     case MSA_W:
-      Lwu(kScratchReg, src);
-      insert_w(dst, laneidx, kScratchReg);
+      Lwu(scratch, src);
+      insert_w(dst, laneidx, scratch);
       break;
     case MSA_D:
-      Ld(kScratchReg, src);
-      insert_d(dst, laneidx, kScratchReg);
+      Ld(scratch, src);
+      insert_d(dst, laneidx, scratch);
       break;
     default:
       UNREACHABLE();
@@ -2657,22 +2659,24 @@ void TurboAssembler::LoadLane(MSASize sz, MSARegister dst, uint8_t laneidx,
 
 void TurboAssembler::StoreLane(MSASize sz, MSARegister src, uint8_t laneidx,
                                MemOperand dst) {
+  UseScratchRegisterScope temps(this);
+  Register scratch = temps.Acquire();
   switch (sz) {
     case MSA_B:
-      copy_u_b(kScratchReg, src, laneidx);
-      Sb(kScratchReg, dst);
+      copy_u_b(scratch, src, laneidx);
+      Sb(scratch, dst);
       break;
     case MSA_H:
-      copy_u_h(kScratchReg, src, laneidx);
-      Sh(kScratchReg, dst);
+      copy_u_h(scratch, src, laneidx);
+      Sh(scratch, dst);
       break;
     case MSA_W:
       if (laneidx == 0) {
         FPURegister src_reg = FPURegister::from_code(src.code());
         Swc1(src_reg, dst);
       } else {
-        copy_u_w(kScratchReg, src, laneidx);
-        Sw(kScratchReg, dst);
+        copy_u_w(scratch, src, laneidx);
+        Sw(scratch, dst);
       }
       break;
     case MSA_D:
@@ -2680,8 +2684,8 @@ void TurboAssembler::StoreLane(MSASize sz, MSARegister src, uint8_t laneidx,
         FPURegister src_reg = FPURegister::from_code(src.code());
         Sdc1(src_reg, dst);
       } else {
-        copy_s_d(kScratchReg, src, laneidx);
-        Sd(kScratchReg, dst);
+        copy_s_d(scratch, src, laneidx);
+        Sd(scratch, dst);
       }
       break;
     default:

src/compiler/backend/mips64/instruction-selector-mips64.cc

@@ -397,36 +397,11 @@ InstructionOperand EmitAddBeforeS128LoadStore(InstructionSelector* selector,
   return addr_reg;
 }
 
-// Helper struct for load lane and store lane to indicate what memory size
-// to be encoded in the opcode, and the new lane index.
-struct LoadStoreLaneParams {
-  MSASize sz;
-  uint8_t laneidx;
-  LoadStoreLaneParams(uint8_t laneidx, MSASize sz, int lanes)
-      : sz(sz), laneidx(laneidx % lanes) {}
-};
-
-LoadStoreLaneParams GetLoadStoreLaneParams(MachineRepresentation rep,
-                                           uint8_t laneidx) {
-  switch (rep) {
-    case MachineRepresentation::kWord8:
-      return LoadStoreLaneParams(laneidx, MSA_B, 16);
-    case MachineRepresentation::kWord16:
-      return LoadStoreLaneParams(laneidx, MSA_H, 8);
-    case MachineRepresentation::kWord32:
-      return LoadStoreLaneParams(laneidx, MSA_W, 4);
-    case MachineRepresentation::kWord64:
-      return LoadStoreLaneParams(laneidx, MSA_D, 2);
-    default:
-      break;
-  }
-  UNREACHABLE();
-}
 }  // namespace
 
 void InstructionSelector::VisitStoreLane(Node* node) {
   StoreLaneParameters params = StoreLaneParametersOf(node->op());
-  LoadStoreLaneParams f = GetLoadStoreLaneParams(params.rep, params.laneidx);
+  LoadStoreLaneParams f(params.rep, params.laneidx);
   InstructionCode opcode = kMips64S128StoreLane;
   opcode |= MiscField::encode(f.sz);
 
@@ -443,8 +418,7 @@ void InstructionSelector::VisitStoreLane(Node* node) {
 
 void InstructionSelector::VisitLoadLane(Node* node) {
   LoadLaneParameters params = LoadLaneParametersOf(node->op());
-  LoadStoreLaneParams f =
-      GetLoadStoreLaneParams(params.rep.representation(), params.laneidx);
+  LoadStoreLaneParams f(params.rep.representation(), params.laneidx);
   InstructionCode opcode = kMips64S128LoadLane;
   opcode |= MiscField::encode(f.sz);
 

src/wasm/baseline/mips/liftoff-assembler-mips.h

@@ -1712,6 +1712,13 @@ void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr,
   bailout(kSimd, "load extend and load splat unimplemented");
 }
 
+void LiftoffAssembler::StoreLane(Register dst, Register offset,
+                                 uintptr_t offset_imm, LiftoffRegister src,
+                                 StoreType type, uint8_t lane,
+                                 uint32_t* protected_store_pc) {
+  bailout(kSimd, "storelane");
+}
+
 void LiftoffAssembler::LoadLane(LiftoffRegister dst, LiftoffRegister src,
                                 Register addr, Register offset_reg,
                                 uintptr_t offset_imm, LoadType type,

src/wasm/baseline/mips64/liftoff-assembler-mips64.h

@@ -6,6 +6,7 @@
 #define V8_WASM_BASELINE_MIPS64_LIFTOFF_ASSEMBLER_MIPS64_H_
 
 #include "src/base/platform/wrappers.h"
+#include "src/codegen/machine-type.h"
 #include "src/heap/memory-chunk.h"
 #include "src/wasm/baseline/liftoff-assembler.h"
 
@@ -1612,7 +1613,20 @@ void LiftoffAssembler::LoadLane(LiftoffRegister dst, LiftoffRegister src,
                                 Register addr, Register offset_reg,
                                 uintptr_t offset_imm, LoadType type,
                                 uint8_t laneidx, uint32_t* protected_load_pc) {
-  bailout(kSimd, "loadlane");
+  MemOperand src_op = liftoff::GetMemOp(this, addr, offset_reg, offset_imm);
+  *protected_load_pc = pc_offset();
+  LoadStoreLaneParams load_params(type.mem_type().representation(), laneidx);
+  TurboAssembler::LoadLane(load_params.sz, dst.fp().toW(), laneidx, src_op);
+}
+
+void LiftoffAssembler::StoreLane(Register dst, Register offset,
+                                 uintptr_t offset_imm, LiftoffRegister src,
+                                 StoreType type, uint8_t lane,
+                                 uint32_t* protected_store_pc) {
+  MemOperand dst_op = liftoff::GetMemOp(this, dst, offset, offset_imm);
+  if (protected_store_pc) *protected_store_pc = pc_offset();
+  LoadStoreLaneParams store_params(type.mem_rep(), lane);
+  TurboAssembler::StoreLane(store_params.sz, src.fp().toW(), lane, dst_op);
 }
 
 void LiftoffAssembler::emit_i8x16_shuffle(LiftoffRegister dst,