Add missing diasm and impl of AVX instr

This change includes splitting the existing SSE_INSTRUCTION_LIST into two:
1. sse instructions with two-operand AVX
2. sse instructions with three-operand AVX

Also a drive by fix for disasm of pblendw, the printing of imm8 doesn't
not require AND-ing with 3, since all 8 bits are significant.

Bug: v8:9561
Change-Id: I56c93a24bb9905ae6422698c793b27f3b9e66d8f
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1933593Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65274}

src/codegen/x64/assembler-x64.cc

@@ -3990,22 +3990,6 @@ void Assembler::pause() {
   emit(0x90);
 }
 
-void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
-  EnsureSpace ensure_space(this);
-  emit_optional_rex_32(dst, src);
-  emit(0x0F);
-  emit(0x5B);
-  emit_sse_operand(dst, src);
-}
-
-void Assembler::cvtdq2ps(XMMRegister dst, Operand src) {
-  EnsureSpace ensure_space(this);
-  emit_optional_rex_32(dst, src);
-  emit(0x0F);
-  emit(0x5B);
-  emit_sse_operand(dst, src);
-}
-
 void Assembler::movups(XMMRegister dst, XMMRegister src) {
   EnsureSpace ensure_space(this);
   if (src.low_bits() == 4) {

src/codegen/x64/assembler-x64.h

@@ -864,7 +864,8 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
     sse_instr(dst, src, 0x##escape, 0x##opcode);             \
   }
 
-  SSE_INSTRUCTION_LIST(DECLARE_SSE_INSTRUCTION)
+  SSE_UNOP_INSTRUCTION_LIST(DECLARE_SSE_INSTRUCTION)
+  SSE_BINOP_INSTRUCTION_LIST(DECLARE_SSE_INSTRUCTION)
 #undef DECLARE_SSE_INSTRUCTION
 
   // SSE instructions with prefix and SSE2 instructions
@@ -1111,8 +1112,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   void pshufhw(XMMRegister dst, Operand src, uint8_t shuffle);
   void pshuflw(XMMRegister dst, XMMRegister src, uint8_t shuffle);
   void pshuflw(XMMRegister dst, Operand src, uint8_t shuffle);
-  void cvtdq2ps(XMMRegister dst, XMMRegister src);
-  void cvtdq2ps(XMMRegister dst, Operand src);
 
   void movlhps(XMMRegister dst, XMMRegister src);
 
@@ -1312,9 +1311,25 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   void vmovdqu(XMMRegister dst, Operand src);
   void vmovdqu(Operand dst, XMMRegister src);
 
-#define AVX_P_3(instr, opcode)  \
-  AVX_3(instr##ps, opcode, vps) \
-  AVX_3(instr##pd, opcode, vpd)
+#define AVX_SSE_UNOP(instr, escape, opcode)          \
+  void v##instr(XMMRegister dst, XMMRegister src2) { \
+    vps(0x##opcode, dst, xmm0, src2);                \
+  }                                                  \
+  void v##instr(XMMRegister dst, Operand src2) {     \
+    vps(0x##opcode, dst, xmm0, src2);                \
+  }
+  SSE_UNOP_INSTRUCTION_LIST(AVX_SSE_UNOP)
+#undef AVX_SSE_UNOP
+
+#define AVX_SSE_BINOP(instr, escape, opcode)                           \
+  void v##instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
+    vps(0x##opcode, dst, src1, src2);                                  \
+  }                                                                    \
+  void v##instr(XMMRegister dst, XMMRegister src1, Operand src2) {     \
+    vps(0x##opcode, dst, src1, src2);                                  \
+  }
+  SSE_BINOP_INSTRUCTION_LIST(AVX_SSE_BINOP)
+#undef AVX_SSE_BINOP
 
 #define AVX_3(instr, opcode, impl)                                  \
   void instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
@@ -1324,17 +1339,9 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
     impl(opcode, dst, src1, src2);                                  \
   }
 
-  AVX_3(vsqrtps, 0x51, vps)
-  AVX_3(vrsqrtps, 0x52, vps)
-  AVX_3(vrcpps, 0x53, vps)
-  AVX_3(vaddps, 0x58, vps)
-  AVX_3(vsubps, 0x5c, vps)
-  AVX_3(vmulps, 0x59, vps)
-  AVX_3(vdivps, 0x5e, vps)
-  AVX_P_3(vand, 0x54)
-  AVX_3(vandnps, 0x55, vps)
-  AVX_P_3(vor, 0x56)
-  AVX_P_3(vxor, 0x57)
+  AVX_3(vandpd, 0x54, vpd)
+  AVX_3(vorpd, 0x56, vpd)
+  AVX_3(vxorpd, 0x57, vpd)
   AVX_3(vcvtsd2ss, 0x5a, vsd)
   AVX_3(vhaddps, 0x7c, vsd)
 
@@ -1350,7 +1357,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
 #undef AVX_SCALAR
 
 #undef AVX_3
-#undef AVX_P_3
 
   void vpsrlq(XMMRegister dst, XMMRegister src, byte imm8) {
     vpd(0x73, xmm2, dst, src);
@@ -1622,12 +1628,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
     vinstr(0x70, dst, xmm0, src, k66, k0F, kWIG);
     emit(imm8);
   }
-  void vcvtdq2ps(XMMRegister dst, XMMRegister src) {
-    vinstr(0x5B, dst, xmm0, src, kNone, k0F, kWIG);
-  }
-  void vcvtdq2ps(XMMRegister dst, Operand src) {
-    vinstr(0x5B, dst, xmm0, src, kNone, k0F, kWIG);
-  }
 
   void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
   void vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2);

src/codegen/x64/sse-instr.h

@@ -5,19 +5,24 @@
 #ifndef V8_CODEGEN_X64_SSE_INSTR_H_
 #define V8_CODEGEN_X64_SSE_INSTR_H_
 
-#define SSE_INSTRUCTION_LIST(V) \
-  V(sqrtps, 0F, 51)             \
-  V(rsqrtps, 0F, 52)            \
-  V(rcpps, 0F, 53)              \
-  V(andps, 0F, 54)              \
-  V(andnps, 0F, 55)             \
-  V(orps, 0F, 56)               \
-  V(xorps, 0F, 57)              \
-  V(addps, 0F, 58)              \
-  V(mulps, 0F, 59)              \
-  V(subps, 0F, 5C)              \
-  V(minps, 0F, 5D)              \
-  V(divps, 0F, 5E)              \
+// SSE instructions whose AVX version has two operands.
+#define SSE_UNOP_INSTRUCTION_LIST(V) \
+  V(sqrtps, 0F, 51)                  \
+  V(rsqrtps, 0F, 52)                 \
+  V(rcpps, 0F, 53)                   \
+  V(cvtdq2ps, 0F, 5B)
+
+// SSE instructions whose AVX version has three operands.
+#define SSE_BINOP_INSTRUCTION_LIST(V) \
+  V(andps, 0F, 54)                    \
+  V(andnps, 0F, 55)                   \
+  V(orps, 0F, 56)                     \
+  V(xorps, 0F, 57)                    \
+  V(addps, 0F, 58)                    \
+  V(mulps, 0F, 59)                    \
+  V(subps, 0F, 5C)                    \
+  V(minps, 0F, 5D)                    \
+  V(divps, 0F, 5E)                    \
   V(maxps, 0F, 5F)
 
 // Instructions dealing with scalar single-precision values.

src/diagnostics/x64/disasm-x64.cc

@@ -1272,25 +1272,32 @@ int DisassemblerX64::AVXInstruction(byte* data) {
         AppendToBuffer("vmovmskps %s,", NameOfCPURegister(regop));
         current += PrintRightXMMOperand(current);
         break;
+      case 0x51:
+      case 0x52:
+      case 0x53:
       case 0x54:
-        AppendToBuffer("vandps %s,%s,", NameOfXMMRegister(regop),
-                       NameOfXMMRegister(vvvv));
-        current += PrintRightXMMOperand(current);
-        break;
       case 0x55:
-        AppendToBuffer("vandnps %s,%s,", NameOfXMMRegister(regop),
-                       NameOfXMMRegister(vvvv));
-        current += PrintRightXMMOperand(current);
-        break;
+      case 0x56:
       case 0x57:
-        AppendToBuffer("vxorps %s,%s,", NameOfXMMRegister(regop),
-                       NameOfXMMRegister(vvvv));
-        current += PrintRightXMMOperand(current);
-        break;
+      case 0x58:
+      case 0x59:
+      case 0x5A:
       case 0x5B:
-        AppendToBuffer("vcvtdq2ps %s,", NameOfXMMRegister(regop));
+      case 0x5C:
+      case 0x5D:
+      case 0x5E:
+      case 0x5F: {
+        const char* const pseudo_op[] = {
+            "vsqrtps",   "vrsqrtps", "vrcpps", "vandps", "vandnps",
+            "vorps",     "vxorps",   "vaddps", "vmulps", "vcvtps2pd",
+            "vcvtdq2ps", "vsubps",   "vminps", "vdivps", "vmaxps",
+        };
+
+        AppendToBuffer("%s %s,%s,", pseudo_op[opcode - 0x51],
+                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
         current += PrintRightXMMOperand(current);
         break;
+      }
       case 0xC2: {
         AppendToBuffer("vcmpps %s,%s,", NameOfXMMRegister(regop),
                        NameOfXMMRegister(vvvv));
@@ -1756,7 +1763,7 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
         get_modrm(*current, &mod, &regop, &rm);
         AppendToBuffer("pblendw %s,", NameOfXMMRegister(regop));
         current += PrintRightXMMOperand(current);
-        AppendToBuffer(",0x%x", (*current) & 3);
+        AppendToBuffer(",0x%x", *current);
         current += 1;
       } else if (third_byte == 0x0F) {
         get_modrm(*current, &mod, &regop, &rm);

test/cctest/test-disasm-x64.cc

@@ -397,7 +397,8 @@ TEST(DisasmX64) {
 #define EMIT_SSE_INSTR(instruction, notUsed1, notUsed2) \
   __ instruction(xmm1, xmm0);                           \
   __ instruction(xmm1, Operand(rbx, rcx, times_4, 10000));
-    SSE_INSTRUCTION_LIST(EMIT_SSE_INSTR)
+    SSE_BINOP_INSTRUCTION_LIST(EMIT_SSE_INSTR)
+    SSE_UNOP_INSTRUCTION_LIST(EMIT_SSE_INSTR)
 #undef EMIT_SSE_INSTR
 
 #define EMIT_SSE_INSTR(instruction, notUsed1, notUsed2, notUse3) \
@@ -710,6 +711,20 @@ TEST(DisasmX64) {
       __ vcmpnlepd(xmm5, xmm4, xmm1);
       __ vcmpnlepd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
 
+#define EMIT_SSE_UNOP_AVXINSTR(instruction, notUsed1, notUsed2) \
+  __ v##instruction(xmm10, xmm1);                               \
+  __ v##instruction(xmm10, Operand(rbx, rcx, times_4, 10000));
+
+      SSE_UNOP_INSTRUCTION_LIST(EMIT_SSE_UNOP_AVXINSTR)
+#undef EMIT_SSE_UNOP_AVXINSTR
+
+#define EMIT_SSE_BINOP_AVXINSTR(instruction, notUsed1, notUsed2) \
+  __ v##instruction(xmm10, xmm5, xmm1);                          \
+  __ v##instruction(xmm10, xmm5, Operand(rbx, rcx, times_4, 10000));
+
+      SSE_BINOP_INSTRUCTION_LIST(EMIT_SSE_BINOP_AVXINSTR)
+#undef EMIT_SSE_BINOP_AVXINSTR
+
 #define EMIT_SSE2_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3) \
   __ v##instruction(xmm10, xmm5, xmm1);                               \
   __ v##instruction(xmm10, xmm5, Operand(rdx, 4));
@@ -749,9 +764,6 @@ TEST(DisasmX64) {
       __ vpinsrd(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 2);
       __ vpshufd(xmm1, xmm2, 85);
       __ vshufps(xmm3, xmm2, xmm3, 3);
-
-      __ vcvtdq2ps(xmm5, xmm1);
-      __ vcvtdq2ps(xmm5, Operand(rdx, 4));
     }
   }