X87: [turbofan] support all shift operands on ia32

port r24387.

original commit message:
  [turbofan] support all shift operands on ia32

BUG=
R=weiliang.lin@intel.com

Review URL: https://codereview.chromium.org/637193002

Patch from Chunyang Dai <chunyang.dai@intel.com>.

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24448 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
parent 8fdae69d
......@@ -915,24 +915,24 @@ void Assembler::rcr(Register dst, uint8_t imm8) {
}
void Assembler::ror(Register dst, uint8_t imm8) {
void Assembler::ror(const Operand& dst, uint8_t imm8) {
EnsureSpace ensure_space(this);
DCHECK(is_uint5(imm8)); // illegal shift count
if (imm8 == 1) {
EMIT(0xD1);
EMIT(0xC8 | dst.code());
emit_operand(ecx, dst);
} else {
EMIT(0xC1);
EMIT(0xC8 | dst.code());
emit_operand(ecx, dst);
EMIT(imm8);
}
}
void Assembler::ror_cl(Register dst) {
void Assembler::ror_cl(const Operand& dst) {
EnsureSpace ensure_space(this);
EMIT(0xD3);
EMIT(0xC8 | dst.code());
emit_operand(ecx, dst);
}
......
......@@ -725,8 +725,11 @@ class Assembler : public AssemblerBase {
void rcl(Register dst, uint8_t imm8);
void rcr(Register dst, uint8_t imm8);
void ror(Register dst, uint8_t imm8);
void ror_cl(Register dst);
void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); }
void ror(const Operand& dst, uint8_t imm8);
void ror_cl(Register dst) { ror_cl(Operand(dst)); }
void ror_cl(const Operand& dst);
void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); }
void sar(const Operand& dst, uint8_t imm8);
......
......@@ -201,6 +201,12 @@ TEST(DisasmIa320) {
__ rcl(edx, 7);
__ rcr(edx, 1);
__ rcr(edx, 7);
__ ror(edx, 1);
__ ror(edx, 6);
__ ror_cl(edx);
__ ror(Operand(ebx, ecx, times_4, 10000), 1);
__ ror(Operand(ebx, ecx, times_4, 10000), 6);
__ ror_cl(Operand(ebx, ecx, times_4, 10000));
__ sar(edx, 1);
__ sar(edx, 6);
__ sar_cl(edx);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment