[Liftoff] Implement float rounding

This adds support for the four rounding operations on f32 and f64:
f32.ceil, f32.floor, f32.trunc, f32.nearest_int, f64.ceil, f64.floor,
f64.trunc, and f64.nearest_int.

R=titzer@chromium.org

Bug: v8:6600
Change-Id: I16ea91e26c3233af7a33bbb794cd4182f9d7cdb0
Reviewed-on: https://chromium-review.googlesource.com/995894
Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
Reviewed-by: Ben Titzer <titzer@chromium.org>
Cr-Commit-Position: refs/heads/master@{#52377}

src/wasm/baseline/arm/liftoff-assembler-arm.h

@@ -156,6 +156,10 @@ UNIMPLEMENTED_FP_BINOP(f32_mul)
 UNIMPLEMENTED_FP_BINOP(f32_div)
 UNIMPLEMENTED_FP_UNOP(f32_abs)
 UNIMPLEMENTED_FP_UNOP(f32_neg)
+UNIMPLEMENTED_FP_UNOP(f32_ceil)
+UNIMPLEMENTED_FP_UNOP(f32_floor)
+UNIMPLEMENTED_FP_UNOP(f32_trunc)
+UNIMPLEMENTED_FP_UNOP(f32_nearest_int)
 UNIMPLEMENTED_FP_UNOP(f32_sqrt)
 UNIMPLEMENTED_FP_BINOP(f64_add)
 UNIMPLEMENTED_FP_BINOP(f64_sub)
@@ -163,6 +167,10 @@ UNIMPLEMENTED_FP_BINOP(f64_mul)
 UNIMPLEMENTED_FP_BINOP(f64_div)
 UNIMPLEMENTED_FP_UNOP(f64_abs)
 UNIMPLEMENTED_FP_UNOP(f64_neg)
+UNIMPLEMENTED_FP_UNOP(f64_ceil)
+UNIMPLEMENTED_FP_UNOP(f64_floor)
+UNIMPLEMENTED_FP_UNOP(f64_trunc)
+UNIMPLEMENTED_FP_UNOP(f64_nearest_int)
 UNIMPLEMENTED_FP_UNOP(f64_sqrt)
 
 #undef UNIMPLEMENTED_GP_BINOP

src/wasm/baseline/arm64/liftoff-assembler-arm64.h

@@ -156,6 +156,10 @@ UNIMPLEMENTED_FP_BINOP(f32_mul)
 UNIMPLEMENTED_FP_BINOP(f32_div)
 UNIMPLEMENTED_FP_UNOP(f32_abs)
 UNIMPLEMENTED_FP_UNOP(f32_neg)
+UNIMPLEMENTED_FP_UNOP(f32_ceil)
+UNIMPLEMENTED_FP_UNOP(f32_floor)
+UNIMPLEMENTED_FP_UNOP(f32_trunc)
+UNIMPLEMENTED_FP_UNOP(f32_nearest_int)
 UNIMPLEMENTED_FP_UNOP(f32_sqrt)
 UNIMPLEMENTED_FP_BINOP(f64_add)
 UNIMPLEMENTED_FP_BINOP(f64_sub)
@@ -163,6 +167,10 @@ UNIMPLEMENTED_FP_BINOP(f64_mul)
 UNIMPLEMENTED_FP_BINOP(f64_div)
 UNIMPLEMENTED_FP_UNOP(f64_abs)
 UNIMPLEMENTED_FP_UNOP(f64_neg)
+UNIMPLEMENTED_FP_UNOP(f64_ceil)
+UNIMPLEMENTED_FP_UNOP(f64_floor)
+UNIMPLEMENTED_FP_UNOP(f64_trunc)
+UNIMPLEMENTED_FP_UNOP(f64_nearest_int)
 UNIMPLEMENTED_FP_UNOP(f64_sqrt)
 
 #undef UNIMPLEMENTED_GP_BINOP

src/wasm/baseline/ia32/liftoff-assembler-ia32.h

@@ -734,6 +734,31 @@ void LiftoffAssembler::emit_f32_neg(DoubleRegister dst, DoubleRegister src) {
   }
 }
 
+void LiftoffAssembler::emit_f32_ceil(DoubleRegister dst, DoubleRegister src) {
+  if (!CpuFeatures::IsSupported(SSE4_1)) return bailout("no sse4.1");
+  CpuFeatureScope feature(this, SSE4_1);
+  roundss(dst, src, kRoundUp);
+}
+
+void LiftoffAssembler::emit_f32_floor(DoubleRegister dst, DoubleRegister src) {
+  if (!CpuFeatures::IsSupported(SSE4_1)) return bailout("no sse4.1");
+  CpuFeatureScope feature(this, SSE4_1);
+  roundss(dst, src, kRoundDown);
+}
+
+void LiftoffAssembler::emit_f32_trunc(DoubleRegister dst, DoubleRegister src) {
+  if (!CpuFeatures::IsSupported(SSE4_1)) return bailout("no sse4.1");
+  CpuFeatureScope feature(this, SSE4_1);
+  roundss(dst, src, kRoundToZero);
+}
+
+void LiftoffAssembler::emit_f32_nearest_int(DoubleRegister dst,
+                                            DoubleRegister src) {
+  if (!CpuFeatures::IsSupported(SSE4_1)) return bailout("no sse4.1");
+  CpuFeatureScope feature(this, SSE4_1);
+  roundss(dst, src, kRoundToNearest);
+}
+
 void LiftoffAssembler::emit_f32_sqrt(DoubleRegister dst, DoubleRegister src) {
   Sqrtss(dst, src);
 }
@@ -816,6 +841,31 @@ void LiftoffAssembler::emit_f64_neg(DoubleRegister dst, DoubleRegister src) {
   }
 }
 
+void LiftoffAssembler::emit_f64_ceil(DoubleRegister dst, DoubleRegister src) {
+  if (!CpuFeatures::IsSupported(SSE4_1)) return bailout("no sse4.1");
+  CpuFeatureScope feature(this, SSE4_1);
+  roundsd(dst, src, kRoundUp);
+}
+
+void LiftoffAssembler::emit_f64_floor(DoubleRegister dst, DoubleRegister src) {
+  if (!CpuFeatures::IsSupported(SSE4_1)) return bailout("no sse4.1");
+  CpuFeatureScope feature(this, SSE4_1);
+  roundsd(dst, src, kRoundDown);
+}
+
+void LiftoffAssembler::emit_f64_trunc(DoubleRegister dst, DoubleRegister src) {
+  if (!CpuFeatures::IsSupported(SSE4_1)) return bailout("no sse4.1");
+  CpuFeatureScope feature(this, SSE4_1);
+  roundsd(dst, src, kRoundToZero);
+}
+
+void LiftoffAssembler::emit_f64_nearest_int(DoubleRegister dst,
+                                            DoubleRegister src) {
+  if (!CpuFeatures::IsSupported(SSE4_1)) return bailout("no sse4.1");
+  CpuFeatureScope feature(this, SSE4_1);
+  roundsd(dst, src, kRoundToNearest);
+}
+
 void LiftoffAssembler::emit_f64_sqrt(DoubleRegister dst, DoubleRegister src) {
   Sqrtsd(dst, src);
 }

src/wasm/baseline/liftoff-assembler.h

@@ -429,6 +429,10 @@ class LiftoffAssembler : public TurboAssembler {
   // f32 unops.
   inline void emit_f32_abs(DoubleRegister dst, DoubleRegister src);
   inline void emit_f32_neg(DoubleRegister dst, DoubleRegister src);
+  inline void emit_f32_ceil(DoubleRegister dst, DoubleRegister src);
+  inline void emit_f32_floor(DoubleRegister dst, DoubleRegister src);
+  inline void emit_f32_trunc(DoubleRegister dst, DoubleRegister src);
+  inline void emit_f32_nearest_int(DoubleRegister dst, DoubleRegister src);
   inline void emit_f32_sqrt(DoubleRegister dst, DoubleRegister src);
 
   // f64 binops.
@@ -444,6 +448,10 @@ class LiftoffAssembler : public TurboAssembler {
   // f64 unops.
   inline void emit_f64_abs(DoubleRegister dst, DoubleRegister src);
   inline void emit_f64_neg(DoubleRegister dst, DoubleRegister src);
+  inline void emit_f64_ceil(DoubleRegister dst, DoubleRegister src);
+  inline void emit_f64_floor(DoubleRegister dst, DoubleRegister src);
+  inline void emit_f64_trunc(DoubleRegister dst, DoubleRegister src);
+  inline void emit_f64_nearest_int(DoubleRegister dst, DoubleRegister src);
   inline void emit_f64_sqrt(DoubleRegister dst, DoubleRegister src);
 
   // type conversions.

src/wasm/baseline/liftoff-compiler.cc

@@ -625,9 +625,17 @@ class LiftoffCompiler {
       CASE_I32_UNOP(I32Ctz, i32_ctz)
       CASE_FLOAT_UNOP(F32Abs, F32, f32_abs)
       CASE_FLOAT_UNOP(F32Neg, F32, f32_neg)
+      CASE_FLOAT_UNOP(F32Ceil, F32, f32_ceil)
+      CASE_FLOAT_UNOP(F32Floor, F32, f32_floor)
+      CASE_FLOAT_UNOP(F32Trunc, F32, f32_trunc)
+      CASE_FLOAT_UNOP(F32NearestInt, F32, f32_nearest_int)
       CASE_FLOAT_UNOP(F32Sqrt, F32, f32_sqrt)
       CASE_FLOAT_UNOP(F64Abs, F64, f64_abs)
       CASE_FLOAT_UNOP(F64Neg, F64, f64_neg)
+      CASE_FLOAT_UNOP(F64Ceil, F64, f64_ceil)
+      CASE_FLOAT_UNOP(F64Floor, F64, f64_floor)
+      CASE_FLOAT_UNOP(F64Trunc, F64, f64_trunc)
+      CASE_FLOAT_UNOP(F64NearestInt, F64, f64_nearest_int)
       CASE_FLOAT_UNOP(F64Sqrt, F64, f64_sqrt)
       CASE_TYPE_CONVERSION(I32ConvertI64, I32, I64, nullptr)
       CASE_TYPE_CONVERSION(I32ReinterpretF32, I32, F32, nullptr)

src/wasm/baseline/mips/liftoff-assembler-mips.h

@@ -528,6 +528,10 @@ FP_BINOP(f32_mul, mul_s)
 FP_BINOP(f32_div, div_s)
 FP_UNOP(f32_abs, abs_s)
 FP_UNOP(f32_neg, neg_s)
+FP_UNOP(f32_ceil, ceil_w_s)
+FP_UNOP(f32_floor, floor_w_s)
+FP_UNOP(f32_trunc, trunc_w_s)
+FP_UNOP(f32_nearest_int, rint_s)
 FP_UNOP(f32_sqrt, sqrt_s)
 FP_BINOP(f64_add, add_d)
 FP_BINOP(f64_sub, sub_d)
@@ -535,6 +539,10 @@ FP_BINOP(f64_mul, mul_d)
 FP_BINOP(f64_div, div_d)
 FP_UNOP(f64_abs, abs_d)
 FP_UNOP(f64_neg, neg_d)
+FP_UNOP(f64_ceil, ceil_w_d)
+FP_UNOP(f64_floor, floor_w_d)
+FP_UNOP(f64_trunc, trunc_w_d)
+FP_UNOP(f64_nearest_int, rint_d)
 FP_UNOP(f64_sqrt, sqrt_d)
 
 #undef FP_BINOP

src/wasm/baseline/mips64/liftoff-assembler-mips64.h

@@ -421,6 +421,10 @@ FP_BINOP(f32_mul, mul_s)
 FP_BINOP(f32_div, div_s)
 FP_UNOP(f32_abs, abs_s)
 FP_UNOP(f32_neg, neg_s)
+FP_UNOP(f32_ceil, ceil_w_s)
+FP_UNOP(f32_floor, floor_w_s)
+FP_UNOP(f32_trunc, trunc_w_s)
+FP_UNOP(f32_nearest_int, rint_s)
 FP_UNOP(f32_sqrt, sqrt_s)
 FP_BINOP(f64_add, add_d)
 FP_BINOP(f64_sub, sub_d)
@@ -428,6 +432,10 @@ FP_BINOP(f64_mul, mul_d)
 FP_BINOP(f64_div, div_d)
 FP_UNOP(f64_abs, abs_d)
 FP_UNOP(f64_neg, neg_d)
+FP_UNOP(f64_ceil, ceil_w_d)
+FP_UNOP(f64_floor, floor_w_d)
+FP_UNOP(f64_trunc, trunc_w_d)
+FP_UNOP(f64_nearest_int, rint_d)
 FP_UNOP(f64_sqrt, sqrt_d)
 
 #undef FP_BINOP

src/wasm/baseline/ppc/liftoff-assembler-ppc.h

@@ -156,6 +156,10 @@ UNIMPLEMENTED_FP_BINOP(f32_mul)
 UNIMPLEMENTED_FP_BINOP(f32_div)
 UNIMPLEMENTED_FP_UNOP(f32_abs)
 UNIMPLEMENTED_FP_UNOP(f32_neg)
+UNIMPLEMENTED_FP_UNOP(f32_ceil)
+UNIMPLEMENTED_FP_UNOP(f32_floor)
+UNIMPLEMENTED_FP_UNOP(f32_trunc)
+UNIMPLEMENTED_FP_UNOP(f32_nearest_int)
 UNIMPLEMENTED_FP_UNOP(f32_sqrt)
 UNIMPLEMENTED_FP_BINOP(f64_add)
 UNIMPLEMENTED_FP_BINOP(f64_sub)
@@ -163,6 +167,10 @@ UNIMPLEMENTED_FP_BINOP(f64_mul)
 UNIMPLEMENTED_FP_BINOP(f64_div)
 UNIMPLEMENTED_FP_UNOP(f64_abs)
 UNIMPLEMENTED_FP_UNOP(f64_neg)
+UNIMPLEMENTED_FP_UNOP(f64_ceil)
+UNIMPLEMENTED_FP_UNOP(f64_floor)
+UNIMPLEMENTED_FP_UNOP(f64_trunc)
+UNIMPLEMENTED_FP_UNOP(f64_nearest_int)
 UNIMPLEMENTED_FP_UNOP(f64_sqrt)
 
 #undef UNIMPLEMENTED_GP_BINOP

src/wasm/baseline/s390/liftoff-assembler-s390.h

@@ -156,6 +156,10 @@ UNIMPLEMENTED_FP_BINOP(f32_mul)
 UNIMPLEMENTED_FP_BINOP(f32_div)
 UNIMPLEMENTED_FP_UNOP(f32_abs)
 UNIMPLEMENTED_FP_UNOP(f32_neg)
+UNIMPLEMENTED_FP_UNOP(f32_ceil)
+UNIMPLEMENTED_FP_UNOP(f32_floor)
+UNIMPLEMENTED_FP_UNOP(f32_trunc)
+UNIMPLEMENTED_FP_UNOP(f32_nearest_int)
 UNIMPLEMENTED_FP_UNOP(f32_sqrt)
 UNIMPLEMENTED_FP_BINOP(f64_add)
 UNIMPLEMENTED_FP_BINOP(f64_sub)
@@ -163,6 +167,10 @@ UNIMPLEMENTED_FP_BINOP(f64_mul)
 UNIMPLEMENTED_FP_BINOP(f64_div)
 UNIMPLEMENTED_FP_UNOP(f64_abs)
 UNIMPLEMENTED_FP_UNOP(f64_neg)
+UNIMPLEMENTED_FP_UNOP(f64_ceil)
+UNIMPLEMENTED_FP_UNOP(f64_floor)
+UNIMPLEMENTED_FP_UNOP(f64_trunc)
+UNIMPLEMENTED_FP_UNOP(f64_nearest_int)
 UNIMPLEMENTED_FP_UNOP(f64_sqrt)
 
 #undef UNIMPLEMENTED_GP_BINOP

src/wasm/baseline/x64/liftoff-assembler-x64.h

@@ -613,6 +613,23 @@ void LiftoffAssembler::emit_f32_neg(DoubleRegister dst, DoubleRegister src) {
   }
 }
 
+void LiftoffAssembler::emit_f32_ceil(DoubleRegister dst, DoubleRegister src) {
+  Roundss(dst, src, kRoundUp);
+}
+
+void LiftoffAssembler::emit_f32_floor(DoubleRegister dst, DoubleRegister src) {
+  Roundss(dst, src, kRoundDown);
+}
+
+void LiftoffAssembler::emit_f32_trunc(DoubleRegister dst, DoubleRegister src) {
+  Roundss(dst, src, kRoundToZero);
+}
+
+void LiftoffAssembler::emit_f32_nearest_int(DoubleRegister dst,
+                                            DoubleRegister src) {
+  Roundss(dst, src, kRoundToNearest);
+}
+
 void LiftoffAssembler::emit_f32_sqrt(DoubleRegister dst, DoubleRegister src) {
   Sqrtss(dst, src);
 }
@@ -695,6 +712,23 @@ void LiftoffAssembler::emit_f64_neg(DoubleRegister dst, DoubleRegister src) {
   }
 }
 
+void LiftoffAssembler::emit_f64_ceil(DoubleRegister dst, DoubleRegister src) {
+  Roundsd(dst, src, kRoundUp);
+}
+
+void LiftoffAssembler::emit_f64_floor(DoubleRegister dst, DoubleRegister src) {
+  Roundsd(dst, src, kRoundDown);
+}
+
+void LiftoffAssembler::emit_f64_trunc(DoubleRegister dst, DoubleRegister src) {
+  Roundsd(dst, src, kRoundToZero);
+}
+
+void LiftoffAssembler::emit_f64_nearest_int(DoubleRegister dst,
+                                            DoubleRegister src) {
+  Roundsd(dst, src, kRoundToNearest);
+}
+
 void LiftoffAssembler::emit_f64_sqrt(DoubleRegister dst, DoubleRegister src) {
   Sqrtsd(dst, src);
 }