[mips][wasm-simd] Prototype i64x2.bitmask

Port: 9d9e8b41

Bug: v8:10997

Change-Id: I147e88d44c65d225ea9f8f27d937fe4b75ff05c4
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2560538
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Reviewed-by: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Auto-Submit: Liu yu <liuyu@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#71513}

src/compiler/backend/instruction-selector.cc

@@ -2824,11 +2824,12 @@ void InstructionSelector::VisitI64x2SignSelect(Node* node) { UNIMPLEMENTED(); }
 #endif  // !V8_TARGET_ARCH_X64
 
 #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_ARM && \
-    !V8_TARGET_ARCH_IA32
+    !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_MIPS64 && !V8_TARGET_ARCH_MIPS
 // TODO(v8:10997) Prototype i64x2.bitmask.
 void InstructionSelector::VisitI64x2BitMask(Node* node) { UNIMPLEMENTED(); }
 #endif  // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_ARM
-        // && !V8_TARGET_ARCH_IA32
+        // && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_MIPS64
+        // && !V8_TARGET_ARCH_MIPS
 
 void InstructionSelector::VisitFinishRegion(Node* node) { EmitIdentity(node); }
 

src/compiler/backend/mips/code-generator-mips.cc

@@ -2260,6 +2260,19 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                 i.InputInt6(1));
       break;
     }
+    case kMipsI64x2BitMask: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      Register dst = i.OutputRegister();
+      Simd128Register src = i.InputSimd128Register(0);
+      Simd128Register scratch0 = kSimd128RegZero;
+      Simd128Register scratch1 = kSimd128ScratchReg;
+      __ srli_d(scratch0, src, 63);
+      __ shf_w(scratch1, scratch0, 0x02);
+      __ slli_d(scratch1, scratch1, 1);
+      __ or_v(scratch0, scratch0, scratch1);
+      __ copy_u_b(dst, scratch0, 0);
+      break;
+    }
     case kMipsF32x4Splat: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       __ FmoveLow(kScratchReg, i.InputSingleRegister(0));

src/compiler/backend/mips/instruction-codes-mips.h

@@ -167,6 +167,7 @@ namespace compiler {
   V(MipsI64x2Shl)                  \
   V(MipsI64x2ShrS)                 \
   V(MipsI64x2ShrU)                 \
+  V(MipsI64x2BitMask)              \
   V(MipsF32x4Splat)                \
   V(MipsF32x4ExtractLane)          \
   V(MipsF32x4ReplaceLane)          \

src/compiler/backend/mips/instruction-scheduler-mips.cc

@@ -70,6 +70,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMipsI64x2Shl:
     case kMipsI64x2ShrS:
     case kMipsI64x2ShrU:
+    case kMipsI64x2BitMask:
     case kMipsF32x4Abs:
     case kMipsF32x4Add:
     case kMipsF32x4AddHoriz:

src/compiler/backend/mips/instruction-selector-mips.cc

@@ -2106,6 +2106,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F64x2Trunc, kMipsF64x2Trunc)                         \
   V(F64x2NearestInt, kMipsF64x2NearestInt)               \
   V(I64x2Neg, kMipsI64x2Neg)                             \
+  V(I64x2BitMask, kMipsI64x2BitMask)                     \
   V(F32x4SConvertI32x4, kMipsF32x4SConvertI32x4)         \
   V(F32x4UConvertI32x4, kMipsF32x4UConvertI32x4)         \
   V(F32x4Abs, kMipsF32x4Abs)                             \
@@ -2120,16 +2121,19 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I32x4SConvertF32x4, kMipsI32x4SConvertF32x4)         \
   V(I32x4UConvertF32x4, kMipsI32x4UConvertF32x4)         \
   V(I32x4Neg, kMipsI32x4Neg)                             \
+  V(I32x4BitMask, kMipsI32x4BitMask)                     \
   V(I32x4SConvertI16x8Low, kMipsI32x4SConvertI16x8Low)   \
   V(I32x4SConvertI16x8High, kMipsI32x4SConvertI16x8High) \
   V(I32x4UConvertI16x8Low, kMipsI32x4UConvertI16x8Low)   \
   V(I32x4UConvertI16x8High, kMipsI32x4UConvertI16x8High) \
   V(I16x8Neg, kMipsI16x8Neg)                             \
+  V(I16x8BitMask, kMipsI16x8BitMask)                     \
   V(I16x8SConvertI8x16Low, kMipsI16x8SConvertI8x16Low)   \
   V(I16x8SConvertI8x16High, kMipsI16x8SConvertI8x16High) \
   V(I16x8UConvertI8x16Low, kMipsI16x8UConvertI8x16Low)   \
   V(I16x8UConvertI8x16High, kMipsI16x8UConvertI8x16High) \
   V(I8x16Neg, kMipsI8x16Neg)                             \
+  V(I8x16BitMask, kMipsI8x16BitMask)                     \
   V(S128Not, kMipsS128Not)                               \
   V(V32x4AnyTrue, kMipsV32x4AnyTrue)                     \
   V(V32x4AllTrue, kMipsV32x4AllTrue)                     \
@@ -2192,7 +2196,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I32x4GtU, kMipsI32x4GtU)                           \
   V(I32x4GeU, kMipsI32x4GeU)                           \
   V(I32x4Abs, kMipsI32x4Abs)                           \
-  V(I32x4BitMask, kMipsI32x4BitMask)                   \
   V(I32x4DotI16x8S, kMipsI32x4DotI16x8S)               \
   V(I16x8Add, kMipsI16x8Add)                           \
   V(I16x8AddSatS, kMipsI16x8AddSatS)                   \
@@ -2216,7 +2219,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I16x8UConvertI32x4, kMipsI16x8UConvertI32x4)       \
   V(I16x8RoundingAverageU, kMipsI16x8RoundingAverageU) \
   V(I16x8Abs, kMipsI16x8Abs)                           \
-  V(I16x8BitMask, kMipsI16x8BitMask)                   \
   V(I8x16Add, kMipsI8x16Add)                           \
   V(I8x16AddSatS, kMipsI8x16AddSatS)                   \
   V(I8x16AddSatU, kMipsI8x16AddSatU)                   \
@@ -2238,7 +2240,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I8x16SConvertI16x8, kMipsI8x16SConvertI16x8)       \
   V(I8x16UConvertI16x8, kMipsI8x16UConvertI16x8)       \
   V(I8x16Abs, kMipsI8x16Abs)                           \
-  V(I8x16BitMask, kMipsI8x16BitMask)                   \
   V(S128And, kMipsS128And)                             \
   V(S128Or, kMipsS128Or)                               \
   V(S128Xor, kMipsS128Xor)                             \

src/compiler/backend/mips64/code-generator-mips64.cc

@@ -2410,6 +2410,19 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       }
       break;
     }
+    case kMips64I64x2BitMask: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      Register dst = i.OutputRegister();
+      Simd128Register src = i.InputSimd128Register(0);
+      Simd128Register scratch0 = kSimd128RegZero;
+      Simd128Register scratch1 = kSimd128ScratchReg;
+      __ srli_d(scratch0, src, 63);
+      __ shf_w(scratch1, scratch0, 0x02);
+      __ slli_d(scratch1, scratch1, 1);
+      __ or_v(scratch0, scratch0, scratch1);
+      __ copy_u_b(dst, scratch0, 0);
+      break;
+    }
     case kMips64F32x4Splat: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       __ FmoveLow(kScratchReg, i.InputSingleRegister(0));

src/compiler/backend/mips64/instruction-codes-mips64.h

@@ -220,6 +220,7 @@ namespace compiler {
   V(Mips64I64x2Shl)                          \
   V(Mips64I64x2ShrS)                         \
   V(Mips64I64x2ShrU)                         \
+  V(Mips64I64x2BitMask)                      \
   V(Mips64F32x4Abs)                          \
   V(Mips64F32x4Neg)                          \
   V(Mips64F32x4Sqrt)                         \

src/compiler/backend/mips64/instruction-scheduler-mips64.cc

@@ -98,6 +98,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMips64I64x2Shl:
     case kMips64I64x2ShrS:
     case kMips64I64x2ShrU:
+    case kMips64I64x2BitMask:
     case kMips64F32x4Abs:
     case kMips64F32x4Add:
     case kMips64F32x4AddHoriz:

src/compiler/backend/mips64/instruction-selector-mips64.cc

@@ -2793,6 +2793,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F64x2Trunc, kMips64F64x2Trunc)                         \
   V(F64x2NearestInt, kMips64F64x2NearestInt)               \
   V(I64x2Neg, kMips64I64x2Neg)                             \
+  V(I64x2BitMask, kMips64I64x2BitMask)                     \
   V(F32x4SConvertI32x4, kMips64F32x4SConvertI32x4)         \
   V(F32x4UConvertI32x4, kMips64F32x4UConvertI32x4)         \
   V(F32x4Abs, kMips64F32x4Abs)                             \

test/cctest/wasm/test-run-wasm-simd.cc

@@ -1631,7 +1631,7 @@ WASM_SIMD_TEST(I32x4BitMask) {
 
 // TODO(v8:10997) Prototyping i64x2.bitmask.
 #if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_ARM || \
-    V8_TARGET_ARCH_IA32
+    V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_MIPS
 WASM_SIMD_TEST_NO_LOWERING(I64x2BitMask) {
   FLAG_SCOPE(wasm_simd_post_mvp);
   WasmRunner<int32_t, int64_t> r(execution_tier, lower_simd);
@@ -1650,7 +1650,7 @@ WASM_SIMD_TEST_NO_LOWERING(I64x2BitMask) {
   }
 }
 #endif  // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_ARM ||
-        // V8_TARGET_ARCH_IA32
+        // V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_MIPS
 
 WASM_SIMD_TEST(I8x16Splat) {
   WasmRunner<int32_t, int32_t> r(execution_tier, lower_simd);