[turbofan][x64] Remove the kX64PeekFloat32 and kX64PeekFloat64 instructions

Instead of these two instructions I generalize the kX64Peek instruction.

R=bmeurer@chromium.org

Change-Id: Ie5f8c7d428b65df3ca8b75594f6a06a75cc8e978
Reviewed-on: https://chromium-review.googlesource.com/839863
Commit-Queue: Andreas Haas <ahaas@chromium.org>
Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Cr-Commit-Position: refs/heads/master@{#50294}

src/compiler/x64/code-generator-x64.cc

@@ -2117,25 +2117,21 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       }
       break;
     }
-    case kX64PeekFloat32: {
-      int reverse_slot = MiscField::decode(instr->opcode());
-      int offset =
-          FrameSlotToFPOffset(frame()->GetTotalFrameSlotCount() - reverse_slot);
-      __ Movss(i.OutputFloatRegister(), Operand(rbp, offset));
-      break;
-    }
-    case kX64PeekFloat64: {
+    case kX64Peek: {
       int reverse_slot = MiscField::decode(instr->opcode());
       int offset =
           FrameSlotToFPOffset(frame()->GetTotalFrameSlotCount() - reverse_slot);
+      if (instr->OutputAt(0)->IsFPRegister()) {
+        LocationOperand* op = LocationOperand::cast(instr->OutputAt(0));
+        if (op->representation() == MachineRepresentation::kFloat64) {
           __ Movsd(i.OutputDoubleRegister(), Operand(rbp, offset));
-      break;
+        } else {
+          DCHECK_EQ(MachineRepresentation::kFloat32, op->representation());
+          __ Movss(i.OutputFloatRegister(), Operand(rbp, offset));
         }
-    case kX64Peek: {
-      int reverse_slot = MiscField::decode(instr->opcode());
-      int offset =
-          FrameSlotToFPOffset(frame()->GetTotalFrameSlotCount() - reverse_slot);
+      } else {
         __ movq(i.OutputRegister(), Operand(rbp, offset));
+      }
       break;
     }
     // TODO(gdeepti): Get rid of redundant moves for F32x4Splat/Extract below

src/compiler/x64/instruction-codes-x64.h

@@ -144,8 +144,6 @@ namespace compiler {
   V(X64Push)                       \
   V(X64Poke)                       \
   V(X64Peek)                       \
-  V(X64PeekFloat32)                \
-  V(X64PeekFloat64)                \
   V(X64StackCheck)                 \
   V(X64F32x4Splat)                 \
   V(X64F32x4ExtractLane)           \

src/compiler/x64/instruction-scheduler-x64.cc

@@ -255,8 +255,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
 
     case kX64StackCheck:
     case kX64Peek:
-    case kX64PeekFloat32:
-    case kX64PeekFloat64:
       return kIsLoadOperation;
 
     case kX64Push:

src/compiler/x64/instruction-selector-x64.cc

@@ -1533,17 +1533,12 @@ void InstructionSelector::EmitPrepareResults(ZoneVector<PushParameter>* results,
     DCHECK(!descriptor->IsCFunctionCall());
     if (output.location.GetType() == MachineType::Float32()) {
       MarkAsFloat32(output.node);
-      InstructionOperand result = g.DefineAsRegister(output.node);
-      Emit(kX64PeekFloat32 | MiscField::encode(reverse_slot), result);
     } else if (output.location.GetType() == MachineType::Float64()) {
       MarkAsFloat64(output.node);
-      InstructionOperand result = g.DefineAsRegister(output.node);
-      Emit(kX64PeekFloat64 | MiscField::encode(reverse_slot), result);
-    } else {
+    }
     InstructionOperand result = g.DefineAsRegister(output.node);
     Emit(kX64Peek | MiscField::encode(reverse_slot), result);
   }
-  }
 }
 
 bool InstructionSelector::IsTailCallAddressImmediate() { return true; }

test/cctest/compiler/test-multiple-return.cc

@@ -517,6 +517,9 @@ void ReturnLastValue(MachineType type) {
 }
 
 TEST(ReturnLastValueInt32) { ReturnLastValue(MachineType::Int32()); }
+#if (!V8_TARGET_ARCH_32_BIT)
+TEST(ReturnLastValueInt64) { ReturnLastValue(MachineType::Int64()); }
+#endif
 TEST(ReturnLastValueFloat32) { ReturnLastValue(MachineType::Float32()); }
 TEST(ReturnLastValueFloat64) { ReturnLastValue(MachineType::Float64()); }