S390: [wasm-simd] Check offset bit count during load/store

The displacement for vlbr and vstbr is a 12-bit unsigned integer.
If a greater offset is passed we must fall back to using
lrvg and strvg.

Change-Id: I34107b82960a4d4de99fbf8b9324b13d9a455e67
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2504190Reviewed-by: Junliang Yan <junyan@redhat.com>
Reviewed-by: Joran Siu <joransiu@ca.ibm.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#70809}

src/compiler/backend/s390/code-generator-s390.cc

@@ -2580,7 +2580,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     case kS390_LoadReverseSimd128: {
       AddressingMode mode = kMode_None;
       MemOperand operand = i.MemoryOperand(&mode);
-      if (CpuFeatures::IsSupported(VECTOR_ENHANCE_FACILITY_2)) {
+      if (CpuFeatures::IsSupported(VECTOR_ENHANCE_FACILITY_2) &&
+          is_uint12(operand.offset())) {
         __ vlbr(i.OutputSimd128Register(), operand, Condition(4));
       } else {
         __ lrvg(r0, operand);
@@ -2642,7 +2643,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       size_t index = 0;
       AddressingMode mode = kMode_None;
       MemOperand operand = i.MemoryOperand(&mode, &index);
-      if (CpuFeatures::IsSupported(VECTOR_ENHANCE_FACILITY_2)) {
+      if (CpuFeatures::IsSupported(VECTOR_ENHANCE_FACILITY_2) &&
+          is_uint12(operand.offset())) {
         __ vstbr(i.InputSimd128Register(index), operand, Condition(4));
       } else {
         __ vlgv(r0, i.InputSimd128Register(index), MemOperand(r0, 1),