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Commit 5097dcb7 authored by Ng Zhi An's avatar Ng Zhi An Committed by Commit Bot
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Specify temp FP/SIMD register 

Change-Id: Icb6a95efd042b116cb495d8bbee1d7261c4f1a05
Bug: v8:9643
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1706128
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: 's avatarDeepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#63879}
parent 2cf821cc
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Showing with 54 additions and 46 deletions
src/compiler/backend/instruction-selector-impl.h
View file @ 5097dcb7
......@@ -264,6 +264,16 @@ class OperandGenerator {
InstructionOperand::kInvalidVirtualRegister);
}
template <typename FPRegType>
InstructionOperand TempFpRegister(FPRegType reg) {
UnallocatedOperand op =
UnallocatedOperand(UnallocatedOperand::FIXED_FP_REGISTER, reg.code(),
sequence()->NextVirtualRegister());
sequence()->MarkAsRepresentation(MachineRepresentation::kSimd128,
op.virtual_register());
return op;
}
InstructionOperand TempImmediate(int32_t imm) {
return sequence()->AddImmediate(Constant(imm));
}
......
src/compiler/backend/x64/code-generator-x64.cc
View file @ 5097dcb7
......@@ -2703,15 +2703,15 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
if (CpuFeatures::IsSupported(SSE4_2)) {
CpuFeatureScope sse_scope_4_2(tasm(), SSE4_2);
XMMRegister dst = i.OutputSimd128Register();
XMMRegister src = i.InputSimd128Register(1);
XMMRegister src0 = i.InputSimd128Register(0);
XMMRegister src1 = i.InputSimd128Register(1);
XMMRegister tmp = i.TempSimd128Register(0);
DCHECK_EQ(dst, i.InputSimd128Register(0));
DCHECK_EQ(src, xmm0);
DCHECK_EQ(tmp, xmm0);
__ movaps(tmp, src);
__ pcmpgtq(src, dst);
__ blendvpd(tmp, dst); // implicit use of xmm0 as mask
__ movaps(dst, tmp);
__ movaps(tmp, src1);
__ pcmpgtq(tmp, src0);
__ movaps(dst, src1);
__ blendvpd(dst, src0); // implicit use of xmm0 as mask
} else {
CpuFeatureScope sse_scope_4_1(tasm(), SSE4_1);
XMMRegister dst = i.OutputSimd128Register();
......@@ -2752,11 +2752,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
XMMRegister src = i.InputSimd128Register(1);
XMMRegister tmp = i.TempSimd128Register(0);
DCHECK_EQ(dst, i.InputSimd128Register(0));
DCHECK_EQ(src, xmm0);
DCHECK_EQ(tmp, xmm0);
__ movaps(tmp, src);
__ pcmpgtq(src, dst);
__ blendvpd(dst, tmp); // implicit use of xmm0 as mask
__ pcmpgtq(tmp, dst);
__ blendvpd(dst, src); // implicit use of xmm0 as mask
break;
}
case kX64I64x2Eq: {
......@@ -2806,24 +2806,23 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
CpuFeatureScope sse_scope_4_2(tasm(), SSE4_2);
CpuFeatureScope sse_scope_4_1(tasm(), SSE4_1);
XMMRegister dst = i.OutputSimd128Register();
XMMRegister src = i.InputSimd128Register(1);
XMMRegister src_tmp = i.TempSimd128Register(0);
XMMRegister dst_tmp = i.TempSimd128Register(1);
DCHECK_EQ(dst, i.InputSimd128Register(0));
DCHECK_EQ(src, xmm0);
XMMRegister src0 = i.InputSimd128Register(0);
XMMRegister src1 = i.InputSimd128Register(1);
XMMRegister tmp0 = i.TempSimd128Register(0);
XMMRegister tmp1 = i.TempSimd128Register(1);
DCHECK_EQ(tmp1, xmm0);
__ movaps(src_tmp, src);
__ movaps(dst_tmp, dst);
__ movaps(dst, src1);
__ movaps(tmp0, src0);
__ pcmpeqd(src, src);
__ psllq(src, 63);
__ pcmpeqd(tmp1, tmp1);
__ psllq(tmp1, 63);
__ pxor(dst_tmp, src);
__ pxor(src, src_tmp);
__ pxor(tmp0, tmp1);
__ pxor(tmp1, dst);
__ pcmpgtq(src, dst_tmp);
__ blendvpd(src_tmp, dst); // implicit use of xmm0 as mask
__ movaps(dst, src_tmp);
__ pcmpgtq(tmp1, tmp0);
__ blendvpd(dst, src0); // implicit use of xmm0 as mask
break;
}
case kX64I64x2MaxU: {
......@@ -2831,22 +2830,21 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
CpuFeatureScope sse_scope_4_1(tasm(), SSE4_1);
XMMRegister dst = i.OutputSimd128Register();
XMMRegister src = i.InputSimd128Register(1);
XMMRegister src_tmp = i.TempSimd128Register(0);
XMMRegister dst_tmp = i.TempSimd128Register(1);
XMMRegister dst_tmp = i.TempSimd128Register(0);
XMMRegister tmp = i.TempSimd128Register(1);
DCHECK_EQ(dst, i.InputSimd128Register(0));
DCHECK_EQ(src, xmm0);
DCHECK_EQ(tmp, xmm0);
__ movaps(src_tmp, src);
__ movaps(dst_tmp, dst);
__ pcmpeqd(src, src);
__ psllq(src, 63);
__ pcmpeqd(tmp, tmp);
__ psllq(tmp, 63);
__ pxor(dst_tmp, src);
__ pxor(src, src_tmp);
__ pxor(dst_tmp, tmp);
__ pxor(tmp, src);
__ pcmpgtq(src, dst_tmp);
__ blendvpd(dst, src_tmp); // implicit use of xmm0 as mask
__ pcmpgtq(tmp, dst_tmp);
__ blendvpd(dst, src); // implicit use of xmm0 as mask
break;
}
case kX64I64x2GtU: {
......
src/compiler/backend/x64/instruction-selector-x64.cc
View file @ 5097dcb7
......@@ -2920,10 +2920,10 @@ void InstructionSelector::VisitI64x2Mul(Node* node) {
void InstructionSelector::VisitI64x2MinS(Node* node) {
X64OperandGenerator g(this);
if (this->IsSupported(SSE4_2)) {
InstructionOperand temps[] = {g.TempSimd128Register()};
Emit(kX64I64x2MinS, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)), g.UseFixed(node->InputAt(1), xmm0),
arraysize(temps), temps);
InstructionOperand temps[] = {g.TempFpRegister(xmm0)};
Emit(kX64I64x2MinS, g.DefineAsRegister(node),
g.UseUniqueRegister(node->InputAt(0)),
g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps);
} else {
InstructionOperand temps[] = {g.TempSimd128Register(), g.TempRegister(),
g.TempRegister()};
......@@ -2935,27 +2935,27 @@ void InstructionSelector::VisitI64x2MinS(Node* node) {
void InstructionSelector::VisitI64x2MaxS(Node* node) {
X64OperandGenerator g(this);
InstructionOperand temps[] = {g.TempSimd128Register()};
InstructionOperand temps[] = {g.TempFpRegister(xmm0)};
Emit(kX64I64x2MaxS, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)), g.UseFixed(node->InputAt(1), xmm0),
g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)),
arraysize(temps), temps);
}
void InstructionSelector::VisitI64x2MinU(Node* node) {
X64OperandGenerator g(this);
InstructionOperand temps[] = {g.TempSimd128Register(),
g.TempSimd128Register()};
Emit(kX64I64x2MinU, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)), g.UseFixed(node->InputAt(1), xmm0),
arraysize(temps), temps);
g.TempFpRegister(xmm0)};
Emit(kX64I64x2MinU, g.DefineAsRegister(node),
g.UseUniqueRegister(node->InputAt(0)),
g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps);
}
void InstructionSelector::VisitI64x2MaxU(Node* node) {
X64OperandGenerator g(this);
InstructionOperand temps[] = {g.TempSimd128Register(),
g.TempSimd128Register()};
g.TempFpRegister(xmm0)};
Emit(kX64I64x2MaxU, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)), g.UseFixed(node->InputAt(1), xmm0),
g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)),
arraysize(temps), temps);
}
......
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