Commit 4ffe9777 authored by sampsong's avatar sampsong Committed by Commit bot

S390: Enable unaligned accesses and character preloading in regexp.

R=joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com, mbrandy@us.ibm.com, bjaideep@ca.ibm.com
BUG=

Review-Url: https://codereview.chromium.org/2072863003
Cr-Commit-Position: refs/heads/master@{#38306}
parent c8241635
...@@ -1232,17 +1232,52 @@ bool RegExpMacroAssemblerS390::CanReadUnaligned() { ...@@ -1232,17 +1232,52 @@ bool RegExpMacroAssemblerS390::CanReadUnaligned() {
void RegExpMacroAssemblerS390::LoadCurrentCharacterUnchecked(int cp_offset, void RegExpMacroAssemblerS390::LoadCurrentCharacterUnchecked(int cp_offset,
int characters) { int characters) {
DCHECK(characters == 1); DCHECK(characters == 1 || CanReadUnaligned());
if (mode_ == LATIN1) { if (mode_ == LATIN1) {
__ LoadlB(current_character(), // using load reverse for big-endian platforms
MemOperand(current_input_offset(), end_of_input_address(), if (characters == 4) {
cp_offset * char_size())); #if V8_TARGET_LITTLE_ENDIAN
__ LoadlW(current_character(),
MemOperand(current_input_offset(), end_of_input_address(),
cp_offset * char_size()));
#else
__ LoadLogicalReversedWordP(current_character(),
MemOperand(current_input_offset(), end_of_input_address(),
cp_offset * char_size()));
#endif
} else if (characters == 2) {
#if V8_TARGET_LITTLE_ENDIAN
__ LoadLogicalHalfWordP(current_character(),
MemOperand(current_input_offset(), end_of_input_address(),
cp_offset * char_size()));
#else
__ LoadLogicalReversedHalfWordP(current_character(),
MemOperand(current_input_offset(), end_of_input_address(),
cp_offset * char_size()));
#endif
} else {
DCHECK(characters == 1);
__ LoadlB(current_character(),
MemOperand(current_input_offset(), end_of_input_address(),
cp_offset * char_size()));
}
} else { } else {
DCHECK(mode_ == UC16); DCHECK(mode_ == UC16);
__ LoadLogicalHalfWordP( if (characters == 2) {
current_character(), __ LoadlW(current_character(),
MemOperand(current_input_offset(), end_of_input_address(), MemOperand(current_input_offset(), end_of_input_address(),
cp_offset * char_size())); cp_offset * char_size()));
#if !V8_TARGET_LITTLE_ENDIAN
// need to swap the order of the characters for big-endian platforms
__ rll(current_character(), current_character(), Operand(16));
#endif
} else {
DCHECK(characters == 1);
__ LoadLogicalHalfWordP(
current_character(),
MemOperand(current_input_offset(), end_of_input_address(),
cp_offset * char_size()));
}
} }
} }
......
...@@ -173,6 +173,7 @@ void CpuFeatures::ProbeImpl(bool cross_compile) { ...@@ -173,6 +173,7 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
USE(performSTFLE); // To avoid assert USE(performSTFLE); // To avoid assert
#endif #endif
supported_ |= (1u << FPU); supported_ |= (1u << FPU);
supported_ |= (1u << UNALIGNED_ACCESSES);
} }
void CpuFeatures::PrintTarget() { void CpuFeatures::PrintTarget() {
......
...@@ -5078,6 +5078,22 @@ void MacroAssembler::LoadlW(Register dst, const MemOperand& mem, ...@@ -5078,6 +5078,22 @@ void MacroAssembler::LoadlW(Register dst, const MemOperand& mem,
#endif #endif
} }
void MacroAssembler::LoadLogicalHalfWordP(Register dst, const MemOperand& mem) {
#if V8_TARGET_ARCH_S390X
llgh(dst, mem);
#else
llh(dst, mem);
#endif
}
void MacroAssembler::LoadLogicalHalfWordP(Register dst, Register src) {
#if V8_TARGET_ARCH_S390X
llghr(dst, src);
#else
llhr(dst, src);
#endif
}
void MacroAssembler::LoadB(Register dst, const MemOperand& mem) { void MacroAssembler::LoadB(Register dst, const MemOperand& mem) {
#if V8_TARGET_ARCH_S390X #if V8_TARGET_ARCH_S390X
lgb(dst, mem); lgb(dst, mem);
...@@ -5102,6 +5118,20 @@ void MacroAssembler::LoadlB(Register dst, const MemOperand& mem) { ...@@ -5102,6 +5118,20 @@ void MacroAssembler::LoadlB(Register dst, const MemOperand& mem) {
#endif #endif
} }
void MacroAssembler::LoadLogicalReversedWordP(Register dst,
const MemOperand& mem) {
lrv(dst, mem);
LoadlW(dst, dst);
}
void MacroAssembler::LoadLogicalReversedHalfWordP(Register dst,
const MemOperand& mem) {
lrvh(dst, mem);
LoadLogicalHalfWordP(dst, dst);
}
// Load And Test (Reg <- Reg) // Load And Test (Reg <- Reg)
void MacroAssembler::LoadAndTest32(Register dst, Register src) { void MacroAssembler::LoadAndTest32(Register dst, Register src) {
ltr(dst, src); ltr(dst, src);
......
...@@ -112,7 +112,6 @@ bool AreAliased(Register reg1, Register reg2, Register reg3 = no_reg, ...@@ -112,7 +112,6 @@ bool AreAliased(Register reg1, Register reg2, Register reg3 = no_reg,
#define LoadRR lgr #define LoadRR lgr
#define LoadAndTestRR ltgr #define LoadAndTestRR ltgr
#define LoadImmP lghi #define LoadImmP lghi
#define LoadLogicalHalfWordP llgh
// Compare // Compare
#define CmpPH cghi #define CmpPH cghi
...@@ -150,7 +149,6 @@ bool AreAliased(Register reg1, Register reg2, Register reg3 = no_reg, ...@@ -150,7 +149,6 @@ bool AreAliased(Register reg1, Register reg2, Register reg3 = no_reg,
#define LoadRR lr #define LoadRR lr
#define LoadAndTestRR ltr #define LoadAndTestRR ltr
#define LoadImmP lhi #define LoadImmP lhi
#define LoadLogicalHalfWordP llh
// Compare // Compare
#define CmpPH chi #define CmpPH chi
...@@ -333,10 +331,15 @@ class MacroAssembler : public Assembler { ...@@ -333,10 +331,15 @@ class MacroAssembler : public Assembler {
void LoadW(Register dst, Register src); void LoadW(Register dst, Register src);
void LoadlW(Register dst, const MemOperand& opnd, Register scratch = no_reg); void LoadlW(Register dst, const MemOperand& opnd, Register scratch = no_reg);
void LoadlW(Register dst, Register src); void LoadlW(Register dst, Register src);
void LoadLogicalHalfWordP(Register dst, const MemOperand& opnd);
void LoadLogicalHalfWordP(Register dst, Register src);
void LoadB(Register dst, const MemOperand& opnd); void LoadB(Register dst, const MemOperand& opnd);
void LoadB(Register dst, Register src); void LoadB(Register dst, Register src);
void LoadlB(Register dst, const MemOperand& opnd); void LoadlB(Register dst, const MemOperand& opnd);
void LoadLogicalReversedWordP(Register dst, const MemOperand& opnd);
void LoadLogicalReversedHalfWordP(Register dst, const MemOperand& opnd);
// Load And Test // Load And Test
void LoadAndTest32(Register dst, Register src); void LoadAndTest32(Register dst, Register src);
void LoadAndTestP_ExtendSrc(Register dst, Register src); void LoadAndTestP_ExtendSrc(Register dst, Register src);
......
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