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Commit 4e68c65a authored by Ng Zhi An's avatar Ng Zhi An Committed by Commit Bot
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[wasm-simd][x64] Use kScratchDoubleReg/kScratchReg instead of temp 

Drive-by cleanups to merge macro lists which now have the same
instruction selector requirements.

Bug: v8:11384
Change-Id: Id49c43dce897685d5ced19509f390274805739aa
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2716069Reviewed-by: 's avatarDeepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#73075}
parent 48406979
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Inline Side-by-side
Showing with 104 additions and 167 deletions
src/codegen/x64/macro-assembler-x64.cc
View file @ 4e68c65a
......@@ -2347,6 +2347,7 @@ void TurboAssembler::I8x16Popcnt(XMMRegister dst, XMMRegister src,
XMMRegister tmp) {
DCHECK_NE(dst, tmp);
DCHECK_NE(src, tmp);
DCHECK_NE(kScratchDoubleReg, tmp);
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope avx_scope(this, AVX);
vmovdqa(tmp, ExternalReferenceAsOperand(
......
src/compiler/backend/x64/instruction-selector-x64.cc
View file @ 4e68c65a
......@@ -2914,22 +2914,20 @@ VISIT_ATOMIC_BINOP(Xor)
V(F32x4AddHoriz) \
V(F32x4Min) \
V(F32x4Max) \
V(I64x2Ne) \
V(I32x4Ne) \
V(I32x4GtU) \
V(I32x4GeS) \
V(I32x4GeU) \
V(I16x8Ne) \
V(I16x8GtU) \
V(I16x8GeS) \
V(I16x8GeU) \
V(I8x16Ne) \
V(I8x16GtU) \
V(I8x16GeS) \
V(I8x16GeU)
#define SIMD_BINOP_ONE_TEMP_LIST(V) \
V(I64x2Ne) \
V(I32x4Ne) \
V(I32x4GtU) \
V(I16x8Ne) \
V(I16x8GtU) \
V(I8x16Ne) \
V(I8x16GtU)
#define SIMD_UNOP_LIST(V) \
V(F64x2Sqrt) \
V(F64x2ConvertLowI32x4S) \
......@@ -2960,9 +2958,14 @@ VISIT_ATOMIC_BINOP(Xor)
V(I16x8UConvertI8x16Low) \
V(I16x8UConvertI8x16High) \
V(I16x8Abs) \
V(I16x8BitMask) \
V(I8x16Neg) \
V(I8x16Abs) \
V(I8x16BitMask) \
V(V64x2AllTrue) \
V(V32x4AllTrue) \
V(V16x8AllTrue) \
V(V8x16AllTrue) \
V(S128Not)
#define SIMD_SHIFT_OPCODES(V) \
......@@ -2979,12 +2982,6 @@ VISIT_ATOMIC_BINOP(Xor)
V(I8x16Shl) \
V(I8x16ShrU)
#define SIMD_ALLTRUE_LIST(V) \
V(V64x2AllTrue) \
V(V32x4AllTrue) \
V(V16x8AllTrue) \
V(V8x16AllTrue)
void InstructionSelector::VisitS128Const(Node* node) {
X64OperandGenerator g(this);
static const int kUint32Immediates = kSimd128Size / sizeof(uint32_t);
......@@ -3086,20 +3083,18 @@ SIMD_TYPES_FOR_REPLACE_LANE(VISIT_SIMD_REPLACE_LANE)
#undef SIMD_TYPES_FOR_REPLACE_LANE
#undef VISIT_SIMD_REPLACE_LANE
#define VISIT_SIMD_SHIFT(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
X64OperandGenerator g(this); \
InstructionOperand dst = IsSupported(AVX) ? g.DefineAsRegister(node) \
: g.DefineSameAsFirst(node); \
if (g.CanBeImmediate(node->InputAt(1))) { \
Emit(kX64##Opcode, dst, g.UseRegister(node->InputAt(0)), \
g.UseImmediate(node->InputAt(1))); \
} else { \
InstructionOperand temps[] = {g.TempSimd128Register(), \
g.TempRegister()}; \
Emit(kX64##Opcode, dst, g.UseUniqueRegister(node->InputAt(0)), \
g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps); \
} \
#define VISIT_SIMD_SHIFT(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
X64OperandGenerator g(this); \
InstructionOperand dst = IsSupported(AVX) ? g.DefineAsRegister(node) \
: g.DefineSameAsFirst(node); \
if (g.CanBeImmediate(node->InputAt(1))) { \
Emit(kX64##Opcode, dst, g.UseRegister(node->InputAt(0)), \
g.UseImmediate(node->InputAt(1))); \
} else { \
Emit(kX64##Opcode, dst, g.UseRegister(node->InputAt(0)), \
g.UseRegister(node->InputAt(1))); \
} \
}
SIMD_SHIFT_OPCODES(VISIT_SIMD_SHIFT)
#undef VISIT_SIMD_SHIFT
......@@ -3158,35 +3153,12 @@ SIMD_BINOP_SSE_AVX_LIST(VISIT_SIMD_BINOP)
#undef VISIT_SIMD_BINOP
#undef SIMD_BINOP_SSE_AVX_LIST
#define VISIT_SIMD_BINOP_ONE_TEMP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
X64OperandGenerator g(this); \
InstructionOperand temps[] = {g.TempSimd128Register()}; \
Emit(kX64##Opcode, g.DefineSameAsFirst(node), \
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), \
arraysize(temps), temps); \
}
SIMD_BINOP_ONE_TEMP_LIST(VISIT_SIMD_BINOP_ONE_TEMP)
#undef VISIT_SIMD_BINOP_ONE_TEMP
#undef SIMD_BINOP_ONE_TEMP_LIST
void InstructionSelector::VisitV128AnyTrue(Node* node) {
X64OperandGenerator g(this);
Emit(kX64V128AnyTrue, g.DefineAsRegister(node),
g.UseUniqueRegister(node->InputAt(0)));
}
#define VISIT_SIMD_ALLTRUE(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
X64OperandGenerator g(this); \
InstructionOperand temps[] = {g.TempSimd128Register()}; \
Emit(kX64##Opcode, g.DefineAsRegister(node), \
g.UseUniqueRegister(node->InputAt(0)), arraysize(temps), temps); \
}
SIMD_ALLTRUE_LIST(VISIT_SIMD_ALLTRUE)
#undef VISIT_SIMD_ALLTRUE
#undef SIMD_ALLTRUE_LIST
void InstructionSelector::VisitS128Select(Node* node) {
X64OperandGenerator g(this);
InstructionOperand dst =
......@@ -3254,20 +3226,12 @@ void InstructionSelector::VisitF32x4UConvertI32x4(Node* node) {
g.UseRegister(node->InputAt(0)));
}
#define VISIT_SIMD_QFMOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
X64OperandGenerator g(this); \
if (CpuFeatures::IsSupported(FMA3)) { \
Emit(kX64##Opcode, g.DefineSameAsFirst(node), \
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), \
g.UseRegister(node->InputAt(2))); \
} else { \
InstructionOperand temps[] = {g.TempSimd128Register()}; \
Emit(kX64##Opcode, g.DefineSameAsFirst(node), \
g.UseUniqueRegister(node->InputAt(0)), \
g.UseUniqueRegister(node->InputAt(1)), \
g.UseRegister(node->InputAt(2)), arraysize(temps), temps); \
} \
#define VISIT_SIMD_QFMOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
X64OperandGenerator g(this); \
Emit(kX64##Opcode, g.DefineSameAsFirst(node), \
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), \
g.UseRegister(node->InputAt(2))); \
}
VISIT_SIMD_QFMOP(F64x2Qfma)
VISIT_SIMD_QFMOP(F64x2Qfms)
......@@ -3286,8 +3250,7 @@ void InstructionSelector::VisitI64x2ShrS(Node* node) {
void InstructionSelector::VisitI64x2Mul(Node* node) {
X64OperandGenerator g(this);
InstructionOperand temps[] = {g.TempSimd128Register(),
g.TempSimd128Register()};
InstructionOperand temps[] = {g.TempSimd128Register()};
Emit(kX64I64x2Mul, g.DefineSameAsFirst(node),
g.UseUniqueRegister(node->InputAt(0)),
g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps);
......@@ -3295,9 +3258,8 @@ void InstructionSelector::VisitI64x2Mul(Node* node) {
void InstructionSelector::VisitI32x4SConvertF32x4(Node* node) {
X64OperandGenerator g(this);
InstructionOperand temps[] = {g.TempSimd128Register()};
Emit(kX64I32x4SConvertF32x4, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)), arraysize(temps), temps);
g.UseRegister(node->InputAt(0)));
}
void InstructionSelector::VisitI32x4UConvertF32x4(Node* node) {
......@@ -3308,13 +3270,6 @@ void InstructionSelector::VisitI32x4UConvertF32x4(Node* node) {
g.UseRegister(node->InputAt(0)), arraysize(temps), temps);
}
void InstructionSelector::VisitI16x8BitMask(Node* node) {
X64OperandGenerator g(this);
InstructionOperand temps[] = {g.TempSimd128Register()};
Emit(kX64I16x8BitMask, g.DefineAsRegister(node),
g.UseUniqueRegister(node->InputAt(0)), arraysize(temps), temps);
}
void InstructionSelector::VisitI8x16ShrS(Node* node) {
X64OperandGenerator g(this);
if (g.CanBeImmediate(node->InputAt(1))) {
......@@ -3710,12 +3665,9 @@ void InstructionSelector::VisitI16x8ExtAddPairwiseI8x16U(Node* node) {
void InstructionSelector::VisitI8x16Popcnt(Node* node) {
X64OperandGenerator g(this);
InstructionOperand dst = CpuFeatures::IsSupported(AVX)
? g.DefineAsRegister(node)
: g.DefineAsRegister(node);
InstructionOperand temps[] = {g.TempSimd128Register()};
Emit(kX64I8x16Popcnt, dst, g.UseUniqueRegister(node->InputAt(0)),
arraysize(temps), temps);
Emit(kX64I8x16Popcnt, g.DefineAsRegister(node),
g.UseUniqueRegister(node->InputAt(0)), arraysize(temps), temps);
}
void InstructionSelector::VisitF64x2ConvertLowI32x4U(Node* node) {
......
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