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Commit 47505486 authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ
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S390 [liftoff]: implement simd shift operations 

This CL implements both the Register-Register and the
Register-Immediate variants needed by liftoff.

Change-Id: I148df8418097004710a17e0b216c2f18db808b8c
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3105085Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#76420}
parent 67b6a9bf
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Showing with 312 additions and 397 deletions
src/codegen/s390/macro-assembler-s390.cc
View file @ 47505486
......@@ -5272,7 +5272,37 @@ SIMD_BINOP_LIST_VRR_C(EMIT_SIMD_BINOP_VRR_C)
#undef EMIT_SIMD_BINOP_VRR_C
#undef SIMD_BINOP_LIST_VRR_C
// Opcodes without a 1-1 match.
#define SIMD_SHIFT_LIST(V) \
V(I64x2Shl, veslv, 3) \
V(I64x2ShrS, vesrav, 3) \
V(I64x2ShrU, vesrlv, 3) \
V(I32x4Shl, veslv, 2) \
V(I32x4ShrS, vesrav, 2) \
V(I32x4ShrU, vesrlv, 2) \
V(I16x8Shl, veslv, 1) \
V(I16x8ShrS, vesrav, 1) \
V(I16x8ShrU, vesrlv, 1) \
V(I8x16Shl, veslv, 0) \
V(I8x16ShrS, vesrav, 0) \
V(I8x16ShrU, vesrlv, 0)
#define EMIT_SIMD_SHIFT(name, op, c1) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
Register src2) { \
vlvg(kScratchDoubleReg, src2, MemOperand(r0, 0), Condition(c1)); \
vrep(kScratchDoubleReg, kScratchDoubleReg, Operand(0), Condition(c1)); \
op(dst, src1, kScratchDoubleReg, Condition(0), Condition(0), \
Condition(c1)); \
} \
void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
const Operand& src2) { \
mov(ip, src2); \
name(dst, src1, ip); \
}
SIMD_SHIFT_LIST(EMIT_SIMD_SHIFT)
#undef EMIT_SIMD_SHIFT
#undef SIMD_SHIFT_LIST
void TurboAssembler::I64x2Mul(Simd128Register dst, Simd128Register src1,
Simd128Register src2) {
Register scratch_1 = r0;
......
src/codegen/s390/macro-assembler-s390.h
View file @ 47505486
......@@ -1070,75 +1070,99 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
void I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx);
#define SIMD_BINOP_LIST(V) \
V(F64x2Add) \
V(F64x2Sub) \
V(F64x2Mul) \
V(F64x2Div) \
V(F64x2Min) \
V(F64x2Max) \
V(F64x2Eq) \
V(F64x2Ne) \
V(F64x2Lt) \
V(F64x2Le) \
V(F32x4Add) \
V(F32x4Sub) \
V(F32x4Mul) \
V(F32x4Div) \
V(F32x4Min) \
V(F32x4Max) \
V(F32x4Eq) \
V(F32x4Ne) \
V(F32x4Lt) \
V(F32x4Le) \
V(I64x2Add) \
V(I64x2Sub) \
V(I64x2Mul) \
V(I64x2Eq) \
V(I64x2Ne) \
V(I64x2GtS) \
V(I64x2GeS) \
V(I32x4Add) \
V(I32x4Sub) \
V(I32x4Mul) \
V(I32x4Eq) \
V(I32x4Ne) \
V(I32x4GtS) \
V(I32x4GeS) \
V(I32x4GtU) \
V(I32x4GeU) \
V(I32x4MinS) \
V(I32x4MinU) \
V(I32x4MaxS) \
V(I32x4MaxU) \
V(I16x8Add) \
V(I16x8Sub) \
V(I16x8Mul) \
V(I16x8Eq) \
V(I16x8Ne) \
V(I16x8GtS) \
V(I16x8GeS) \
V(I16x8GtU) \
V(I16x8GeU) \
V(I16x8MinS) \
V(I16x8MinU) \
V(I16x8MaxS) \
V(I16x8MaxU) \
V(I8x16Add) \
V(I8x16Sub) \
V(I8x16Eq) \
V(I8x16Ne) \
V(I8x16GtS) \
V(I8x16GeS) \
V(I8x16GtU) \
V(I8x16GeU) \
V(I8x16MinS) \
V(I8x16MinU) \
V(I8x16MaxS) \
V(I8x16MaxU)
#define PROTOTYPE_SIMD_BINOP(name) \
void name(Simd128Register dst, Simd128Register src1, Simd128Register src2);
#define SIMD_BINOP_LIST(V) \
V(F64x2Add, Simd128Register) \
V(F64x2Sub, Simd128Register) \
V(F64x2Mul, Simd128Register) \
V(F64x2Div, Simd128Register) \
V(F64x2Min, Simd128Register) \
V(F64x2Max, Simd128Register) \
V(F64x2Eq, Simd128Register) \
V(F64x2Ne, Simd128Register) \
V(F64x2Lt, Simd128Register) \
V(F64x2Le, Simd128Register) \
V(F32x4Add, Simd128Register) \
V(F32x4Sub, Simd128Register) \
V(F32x4Mul, Simd128Register) \
V(F32x4Div, Simd128Register) \
V(F32x4Min, Simd128Register) \
V(F32x4Max, Simd128Register) \
V(F32x4Eq, Simd128Register) \
V(F32x4Ne, Simd128Register) \
V(F32x4Lt, Simd128Register) \
V(F32x4Le, Simd128Register) \
V(I64x2Add, Simd128Register) \
V(I64x2Sub, Simd128Register) \
V(I64x2Mul, Simd128Register) \
V(I64x2Eq, Simd128Register) \
V(I64x2Ne, Simd128Register) \
V(I64x2GtS, Simd128Register) \
V(I64x2GeS, Simd128Register) \
V(I64x2Shl, Register) \
V(I64x2ShrS, Register) \
V(I64x2ShrU, Register) \
V(I64x2Shl, const Operand&) \
V(I64x2ShrS, const Operand&) \
V(I64x2ShrU, const Operand&) \
V(I32x4Add, Simd128Register) \
V(I32x4Sub, Simd128Register) \
V(I32x4Mul, Simd128Register) \
V(I32x4Eq, Simd128Register) \
V(I32x4Ne, Simd128Register) \
V(I32x4GtS, Simd128Register) \
V(I32x4GeS, Simd128Register) \
V(I32x4GtU, Simd128Register) \
V(I32x4GeU, Simd128Register) \
V(I32x4MinS, Simd128Register) \
V(I32x4MinU, Simd128Register) \
V(I32x4MaxS, Simd128Register) \
V(I32x4MaxU, Simd128Register) \
V(I32x4Shl, Register) \
V(I32x4ShrS, Register) \
V(I32x4ShrU, Register) \
V(I32x4Shl, const Operand&) \
V(I32x4ShrS, const Operand&) \
V(I32x4ShrU, const Operand&) \
V(I16x8Add, Simd128Register) \
V(I16x8Sub, Simd128Register) \
V(I16x8Mul, Simd128Register) \
V(I16x8Eq, Simd128Register) \
V(I16x8Ne, Simd128Register) \
V(I16x8GtS, Simd128Register) \
V(I16x8GeS, Simd128Register) \
V(I16x8GtU, Simd128Register) \
V(I16x8GeU, Simd128Register) \
V(I16x8MinS, Simd128Register) \
V(I16x8MinU, Simd128Register) \
V(I16x8MaxS, Simd128Register) \
V(I16x8MaxU, Simd128Register) \
V(I16x8Shl, Register) \
V(I16x8ShrS, Register) \
V(I16x8ShrU, Register) \
V(I16x8Shl, const Operand&) \
V(I16x8ShrS, const Operand&) \
V(I16x8ShrU, const Operand&) \
V(I8x16Add, Simd128Register) \
V(I8x16Sub, Simd128Register) \
V(I8x16Eq, Simd128Register) \
V(I8x16Ne, Simd128Register) \
V(I8x16GtS, Simd128Register) \
V(I8x16GeS, Simd128Register) \
V(I8x16GtU, Simd128Register) \
V(I8x16GeU, Simd128Register) \
V(I8x16MinS, Simd128Register) \
V(I8x16MinU, Simd128Register) \
V(I8x16MaxS, Simd128Register) \
V(I8x16MaxU, Simd128Register) \
V(I8x16Shl, Register) \
V(I8x16ShrS, Register) \
V(I8x16ShrU, Register) \
V(I8x16Shl, const Operand&) \
V(I8x16ShrS, const Operand&) \
V(I8x16ShrU, const Operand&)
#define PROTOTYPE_SIMD_BINOP(name, stype) \
void name(Simd128Register dst, Simd128Register src1, stype src2);
SIMD_BINOP_LIST(PROTOTYPE_SIMD_BINOP)
#undef PROTOTYPE_SIMD_BINOP
#undef SIMD_BINOP_LIST
......
src/compiler/backend/s390/code-generator-s390.cc
View file @ 47505486
......@@ -2426,77 +2426,89 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
ASSEMBLE_ATOMIC64_COMP_EXCHANGE_WORD64();
break;
// Simd Support.
#define SIMD_BINOP_LIST(V) \
V(F64x2Add) \
V(F64x2Sub) \
V(F64x2Mul) \
V(F64x2Div) \
V(F64x2Min) \
V(F64x2Max) \
V(F64x2Eq) \
V(F64x2Ne) \
V(F64x2Lt) \
V(F64x2Le) \
V(F32x4Add) \
V(F32x4Sub) \
V(F32x4Mul) \
V(F32x4Div) \
V(F32x4Min) \
V(F32x4Max) \
V(F32x4Eq) \
V(F32x4Ne) \
V(F32x4Lt) \
V(F32x4Le) \
V(I64x2Add) \
V(I64x2Sub) \
V(I64x2Mul) \
V(I64x2Eq) \
V(I64x2Ne) \
V(I64x2GtS) \
V(I64x2GeS) \
V(I32x4Add) \
V(I32x4Sub) \
V(I32x4Mul) \
V(I32x4Eq) \
V(I32x4Ne) \
V(I32x4GtS) \
V(I32x4GeS) \
V(I32x4GtU) \
V(I32x4GeU) \
V(I32x4MinS) \
V(I32x4MinU) \
V(I32x4MaxS) \
V(I32x4MaxU) \
V(I16x8Add) \
V(I16x8Sub) \
V(I16x8Mul) \
V(I16x8Eq) \
V(I16x8Ne) \
V(I16x8GtS) \
V(I16x8GeS) \
V(I16x8GtU) \
V(I16x8GeU) \
V(I16x8MinS) \
V(I16x8MinU) \
V(I16x8MaxS) \
V(I16x8MaxU) \
V(I8x16Add) \
V(I8x16Sub) \
V(I8x16Eq) \
V(I8x16Ne) \
V(I8x16GtS) \
V(I8x16GeS) \
V(I8x16GtU) \
V(I8x16GeU) \
V(I8x16MinS) \
V(I8x16MinU) \
V(I8x16MaxS) \
V(I8x16MaxU)
#define EMIT_SIMD_BINOP(name) \
#define SIMD_BINOP_LIST(V) \
V(F64x2Add, Simd128Register) \
V(F64x2Sub, Simd128Register) \
V(F64x2Mul, Simd128Register) \
V(F64x2Div, Simd128Register) \
V(F64x2Min, Simd128Register) \
V(F64x2Max, Simd128Register) \
V(F64x2Eq, Simd128Register) \
V(F64x2Ne, Simd128Register) \
V(F64x2Lt, Simd128Register) \
V(F64x2Le, Simd128Register) \
V(F32x4Add, Simd128Register) \
V(F32x4Sub, Simd128Register) \
V(F32x4Mul, Simd128Register) \
V(F32x4Div, Simd128Register) \
V(F32x4Min, Simd128Register) \
V(F32x4Max, Simd128Register) \
V(F32x4Eq, Simd128Register) \
V(F32x4Ne, Simd128Register) \
V(F32x4Lt, Simd128Register) \
V(F32x4Le, Simd128Register) \
V(I64x2Add, Simd128Register) \
V(I64x2Sub, Simd128Register) \
V(I64x2Mul, Simd128Register) \
V(I64x2Eq, Simd128Register) \
V(I64x2Ne, Simd128Register) \
V(I64x2GtS, Simd128Register) \
V(I64x2GeS, Simd128Register) \
V(I64x2Shl, Register) \
V(I64x2ShrS, Register) \
V(I64x2ShrU, Register) \
V(I32x4Add, Simd128Register) \
V(I32x4Sub, Simd128Register) \
V(I32x4Mul, Simd128Register) \
V(I32x4Eq, Simd128Register) \
V(I32x4Ne, Simd128Register) \
V(I32x4GtS, Simd128Register) \
V(I32x4GeS, Simd128Register) \
V(I32x4GtU, Simd128Register) \
V(I32x4GeU, Simd128Register) \
V(I32x4MinS, Simd128Register) \
V(I32x4MinU, Simd128Register) \
V(I32x4MaxS, Simd128Register) \
V(I32x4MaxU, Simd128Register) \
V(I32x4Shl, Register) \
V(I32x4ShrS, Register) \
V(I32x4ShrU, Register) \
V(I16x8Add, Simd128Register) \
V(I16x8Sub, Simd128Register) \
V(I16x8Mul, Simd128Register) \
V(I16x8Eq, Simd128Register) \
V(I16x8Ne, Simd128Register) \
V(I16x8GtS, Simd128Register) \
V(I16x8GeS, Simd128Register) \
V(I16x8GtU, Simd128Register) \
V(I16x8GeU, Simd128Register) \
V(I16x8MinS, Simd128Register) \
V(I16x8MinU, Simd128Register) \
V(I16x8MaxS, Simd128Register) \
V(I16x8MaxU, Simd128Register) \
V(I16x8Shl, Register) \
V(I16x8ShrS, Register) \
V(I16x8ShrU, Register) \
V(I8x16Add, Simd128Register) \
V(I8x16Sub, Simd128Register) \
V(I8x16Eq, Simd128Register) \
V(I8x16Ne, Simd128Register) \
V(I8x16GtS, Simd128Register) \
V(I8x16GeS, Simd128Register) \
V(I8x16GtU, Simd128Register) \
V(I8x16GeU, Simd128Register) \
V(I8x16MinS, Simd128Register) \
V(I8x16MinU, Simd128Register) \
V(I8x16MaxS, Simd128Register) \
V(I8x16MaxU, Simd128Register) \
V(I8x16Shl, Register) \
V(I8x16ShrS, Register) \
V(I8x16ShrU, Register)
#define EMIT_SIMD_BINOP(name, stype) \
case kS390_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.InputSimd128Register(1)); \
i.Input##stype(1)); \
break; \
}
SIMD_BINOP_LIST(EMIT_SIMD_BINOP)
......@@ -2601,64 +2613,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(0));
break;
}
// vector shifts
#define VECTOR_SHIFT(op, mode) \
{ \
__ vlvg(kScratchDoubleReg, i.InputRegister(1), MemOperand(r0, 0), \
Condition(mode)); \
__ vrep(kScratchDoubleReg, kScratchDoubleReg, Operand(0), \
Condition(mode)); \
__ op(i.OutputSimd128Register(), i.InputSimd128Register(0), \
kScratchDoubleReg, Condition(0), Condition(0), Condition(mode)); \
}
case kS390_I64x2Shl: {
VECTOR_SHIFT(veslv, 3);
break;
}
case kS390_I64x2ShrS: {
VECTOR_SHIFT(vesrav, 3);
break;
}
case kS390_I64x2ShrU: {
VECTOR_SHIFT(vesrlv, 3);
break;
}
case kS390_I32x4Shl: {
VECTOR_SHIFT(veslv, 2);
break;
}
case kS390_I32x4ShrS: {
VECTOR_SHIFT(vesrav, 2);
break;
}
case kS390_I32x4ShrU: {
VECTOR_SHIFT(vesrlv, 2);
break;
}
case kS390_I16x8Shl: {
VECTOR_SHIFT(veslv, 1);
break;
}
case kS390_I16x8ShrS: {
VECTOR_SHIFT(vesrav, 1);
break;
}
case kS390_I16x8ShrU: {
VECTOR_SHIFT(vesrlv, 1);
break;
}
case kS390_I8x16Shl: {
VECTOR_SHIFT(veslv, 0);
break;
}
case kS390_I8x16ShrS: {
VECTOR_SHIFT(vesrav, 0);
break;
}
case kS390_I8x16ShrU: {
VECTOR_SHIFT(vesrlv, 0);
break;
}
// vector unary ops
case kS390_F64x2Abs: {
__ vfpso(i.OutputSimd128Register(), i.InputSimd128Register(0),
......
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