Commit 4629bc06 authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ

PPC/s390: Reland "[compiler] Support acq/rel accesses and atomic accesses on tagged"

Port 6a487504

Original Commit Message:

    This is a reland of faf2208a

    Changes since revert:
    - Fix arm64 codegen for full pointer mode

    Original change's description:
    > [compiler] Support acq/rel accesses and atomic accesses on tagged
    >
    > This CL adds an AtomicMemoryOrder parameter to the various atomic load
    > and store operators. Currently only acquire release (kAcqRel) and
    > sequentially consistent (kSeqCst) orders are supported.
    >
    > Additionally, atomic loads and stores are extended to work with tagged
    > values.
    >
    > This CL is a pre-requisite for supporting atomic accesses in Torque,
    > which is in turn a pre-requisite for prototyping shared strings.
    >
    > Bug: v8:11995
    > Change-Id: Ic77d2640e2dc7e5581b1211a054c93210c219355
    > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3101765
    > Reviewed-by: Nico Hartmann <nicohartmann@chromium.org>
    > Reviewed-by: Zhi An Ng <zhin@chromium.org>
    > Commit-Queue: Shu-yu Guo <syg@chromium.org>
    > Cr-Commit-Position: refs/heads/main@{#76393}

R=syg@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com
BUG=
LOG=N

Change-Id: I859320f1e752a8e79a0855ecad8651c635092f46
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3108289Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/main@{#76407}
parent c52236ab
......@@ -252,24 +252,23 @@ void InstructionSelector::VisitProtectedLoad(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitStore(Node* node) {
PPCOperandGenerator g(this);
void VisitStoreCommon(InstructionSelector* selector, Node* node,
StoreRepresentation store_rep,
base::Optional<AtomicMemoryOrder> atomic_order) {
PPCOperandGenerator g(selector);
Node* base = node->InputAt(0);
Node* offset = node->InputAt(1);
Node* value = node->InputAt(2);
// TODO(miladfarca): maybe use atomic_order?
bool is_atomic = (node->opcode() == IrOpcode::kWord32AtomicStore ||
node->opcode() == IrOpcode::kWord64AtomicStore);
MachineRepresentation rep;
MachineRepresentation rep = store_rep.representation();
WriteBarrierKind write_barrier_kind = kNoWriteBarrier;
if (is_atomic) {
rep = AtomicStoreRepresentationOf(node->op());
} else {
StoreRepresentation store_rep = StoreRepresentationOf(node->op());
if (!is_atomic) {
write_barrier_kind = store_rep.write_barrier_kind();
rep = store_rep.representation();
}
if (FLAG_enable_unconditional_write_barriers &&
......@@ -305,7 +304,7 @@ void InstructionSelector::VisitStore(Node* node) {
code |= AddressingModeField::encode(addressing_mode);
code |= MiscField::encode(static_cast<int>(record_write_mode));
CHECK_EQ(is_atomic, false);
Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
selector->Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
} else {
ArchOpcode opcode;
ImmediateMode mode = kInt16Imm;
......@@ -367,21 +366,26 @@ void InstructionSelector::VisitStore(Node* node) {
}
if (g.CanBeImmediate(offset, mode)) {
Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
g.UseRegister(base), g.UseImmediate(offset), g.UseRegister(value),
g.UseImmediate(is_atomic));
selector->Emit(opcode | AddressingModeField::encode(kMode_MRI),
g.NoOutput(), g.UseRegister(base), g.UseImmediate(offset),
g.UseRegister(value), g.UseImmediate(is_atomic));
} else if (g.CanBeImmediate(base, mode)) {
Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
g.UseRegister(offset), g.UseImmediate(base), g.UseRegister(value),
g.UseImmediate(is_atomic));
selector->Emit(opcode | AddressingModeField::encode(kMode_MRI),
g.NoOutput(), g.UseRegister(offset), g.UseImmediate(base),
g.UseRegister(value), g.UseImmediate(is_atomic));
} else {
Emit(opcode | AddressingModeField::encode(kMode_MRR), g.NoOutput(),
g.UseRegister(base), g.UseRegister(offset), g.UseRegister(value),
g.UseImmediate(is_atomic));
selector->Emit(opcode | AddressingModeField::encode(kMode_MRR),
g.NoOutput(), g.UseRegister(base), g.UseRegister(offset),
g.UseRegister(value), g.UseImmediate(is_atomic));
}
}
}
void InstructionSelector::VisitStore(Node* node) {
VisitStoreCommon(this, node, StoreRepresentationOf(node->op()),
base::nullopt);
}
void InstructionSelector::VisitProtectedStore(Node* node) {
// TODO(eholk)
UNIMPLEMENTED();
......@@ -1954,11 +1958,15 @@ void InstructionSelector::VisitWord32AtomicLoad(Node* node) { VisitLoad(node); }
void InstructionSelector::VisitWord64AtomicLoad(Node* node) { VisitLoad(node); }
void InstructionSelector::VisitWord32AtomicStore(Node* node) {
VisitStore(node);
AtomicStoreParameters store_params = AtomicStoreParametersOf(node->op());
VisitStoreCommon(this, node, store_params.store_representation(),
store_params.order());
}
void InstructionSelector::VisitWord64AtomicStore(Node* node) {
VisitStore(node);
AtomicStoreParameters store_params = AtomicStoreParametersOf(node->op());
VisitStoreCommon(this, node, store_params.store_representation(),
store_params.order());
}
void VisitAtomicExchange(InstructionSelector* selector, Node* node,
......
......@@ -2156,8 +2156,8 @@ void InstructionSelector::VisitWord32AtomicLoad(Node* node) {
}
void InstructionSelector::VisitWord32AtomicStore(Node* node) {
MachineRepresentation rep = AtomicStoreRepresentationOf(node->op());
VisitGeneralStore(this, node, rep);
AtomicStoreParameters store_params = AtomicStoreParametersOf(node->op());
VisitGeneralStore(this, node, store_params.representation());
}
void VisitAtomicExchange(InstructionSelector* selector, Node* node,
......@@ -2395,8 +2395,8 @@ void InstructionSelector::VisitWord64AtomicLoad(Node* node) {
}
void InstructionSelector::VisitWord64AtomicStore(Node* node) {
MachineRepresentation rep = AtomicStoreRepresentationOf(node->op());
VisitGeneralStore(this, node, rep);
AtomicStoreParameters store_params = AtomicStoreParametersOf(node->op());
VisitGeneralStore(this, node, store_params.representation());
}
#define SIMD_TYPES(V) \
......
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