Commit 45125492 authored by Milad Fa's avatar Milad Fa Committed by Commit Bot

PPC [simd]: Implement vector shift ops on Sim

Change-Id: I051a82a4a041aa81c150ce559b2b3cbee7718425
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2727271Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#73143}
parent f7a23f44
......@@ -3974,6 +3974,65 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
break;
}
#undef VECTOR_MIN_MAX_OP
#define VECTOR_SHIFT_OP(type, op, mask) \
int t = instr->RSValue(); \
int a = instr->RAValue(); \
int b = instr->RBValue(); \
FOR_EACH_LANE(i, type) { \
set_simd_register_by_lane<type>( \
t, i, \
get_simd_register_by_lane<type>(a, i) \
op(get_simd_register_by_lane<type>(b, i) & mask)); \
}
case VSLD: {
VECTOR_SHIFT_OP(int64_t, <<, 0x3f)
break;
}
case VSRAD: {
VECTOR_SHIFT_OP(int64_t, >>, 0x3f)
break;
}
case VSRD: {
VECTOR_SHIFT_OP(uint64_t, >>, 0x3f)
break;
}
case VSLW: {
VECTOR_SHIFT_OP(int32_t, <<, 0x1f)
break;
}
case VSRAW: {
VECTOR_SHIFT_OP(int32_t, >>, 0x1f)
break;
}
case VSRW: {
VECTOR_SHIFT_OP(uint32_t, >>, 0x1f)
break;
}
case VSLH: {
VECTOR_SHIFT_OP(int16_t, <<, 0xf)
break;
}
case VSRAH: {
VECTOR_SHIFT_OP(int16_t, >>, 0xf)
break;
}
case VSRH: {
VECTOR_SHIFT_OP(uint16_t, >>, 0xf)
break;
}
case VSLB: {
VECTOR_SHIFT_OP(int8_t, <<, 0x7)
break;
}
case VSRAB: {
VECTOR_SHIFT_OP(int8_t, >>, 0x7)
break;
}
case VSRB: {
VECTOR_SHIFT_OP(uint8_t, >>, 0x7)
break;
}
#undef VECTOR_SHIFT_OP
#undef FOR_EACH_LANE
default: {
UNIMPLEMENTED();
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment