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Commit 429f959f authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ
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PPC [liftoff]: Implement simd comparison ops 

Change-Id: Id691009bddafdbb5a53c234fe00995b6e0733586
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3893417
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/main@{#83200}
parent 35e58232
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Showing with 303 additions and 302 deletions
src/codegen/ppc/macro-assembler-ppc.cc
View file @ 429f959f
...@@ -3684,14 +3684,18 @@ void TurboAssembler::StoreF32LE(DoubleRegister dst, const MemOperand& mem, ...@@ -3684,14 +3684,18 @@ void TurboAssembler::StoreF32LE(DoubleRegister dst, const MemOperand& mem,
V(F64x2Sub, xvsubdp) \ V(F64x2Sub, xvsubdp) \
V(F64x2Mul, xvmuldp) \ V(F64x2Mul, xvmuldp) \
V(F64x2Div, xvdivdp) \ V(F64x2Div, xvdivdp) \
V(F64x2Eq, xvcmpeqdp) \
V(F32x4Add, vaddfp) \ V(F32x4Add, vaddfp) \
V(F32x4Sub, vsubfp) \ V(F32x4Sub, vsubfp) \
V(F32x4Mul, xvmulsp) \ V(F32x4Mul, xvmulsp) \
V(F32x4Div, xvdivsp) \ V(F32x4Div, xvdivsp) \
V(F32x4Min, vminfp) \ V(F32x4Min, vminfp) \
V(F32x4Max, vmaxfp) \ V(F32x4Max, vmaxfp) \
V(F32x4Eq, xvcmpeqsp) \
V(I64x2Add, vaddudm) \ V(I64x2Add, vaddudm) \
V(I64x2Sub, vsubudm) \ V(I64x2Sub, vsubudm) \
V(I64x2Eq, vcmpequd) \
V(I64x2GtS, vcmpgtsd) \
V(I32x4Add, vadduwm) \ V(I32x4Add, vadduwm) \
V(I32x4Sub, vsubuwm) \ V(I32x4Sub, vsubuwm) \
V(I32x4Mul, vmuluwm) \ V(I32x4Mul, vmuluwm) \
...@@ -3699,18 +3703,27 @@ void TurboAssembler::StoreF32LE(DoubleRegister dst, const MemOperand& mem, ...@@ -3699,18 +3703,27 @@ void TurboAssembler::StoreF32LE(DoubleRegister dst, const MemOperand& mem,
V(I32x4MinU, vminuw) \ V(I32x4MinU, vminuw) \
V(I32x4MaxS, vmaxsw) \ V(I32x4MaxS, vmaxsw) \
V(I32x4MaxU, vmaxuw) \ V(I32x4MaxU, vmaxuw) \
V(I32x4Eq, vcmpequw) \
V(I32x4GtS, vcmpgtsw) \
V(I32x4GtU, vcmpgtuw) \
V(I16x8Add, vadduhm) \ V(I16x8Add, vadduhm) \
V(I16x8Sub, vsubuhm) \ V(I16x8Sub, vsubuhm) \
V(I16x8MinS, vminsh) \ V(I16x8MinS, vminsh) \
V(I16x8MinU, vminuh) \ V(I16x8MinU, vminuh) \
V(I16x8MaxS, vmaxsh) \ V(I16x8MaxS, vmaxsh) \
V(I16x8MaxU, vmaxuh) \ V(I16x8MaxU, vmaxuh) \
V(I16x8Eq, vcmpequh) \
V(I16x8GtS, vcmpgtsh) \
V(I16x8GtU, vcmpgtuh) \
V(I8x16Add, vaddubm) \ V(I8x16Add, vaddubm) \
V(I8x16Sub, vsububm) \ V(I8x16Sub, vsububm) \
V(I8x16MinS, vminsb) \ V(I8x16MinS, vminsb) \
V(I8x16MinU, vminub) \ V(I8x16MinU, vminub) \
V(I8x16MaxS, vmaxsb) \ V(I8x16MaxS, vmaxsb) \
V(I8x16MaxU, vmaxub) V(I8x16MaxU, vmaxub) \
V(I8x16Eq, vcmpequb) \
V(I8x16GtS, vcmpgtsb) \
V(I8x16GtU, vcmpgtub)
#define EMIT_SIMD_BINOP(name, op) \ #define EMIT_SIMD_BINOP(name, op) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \ void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
...@@ -3996,6 +4009,107 @@ void TurboAssembler::F64x2Max(Simd128Register dst, Simd128Register src1, ...@@ -3996,6 +4009,107 @@ void TurboAssembler::F64x2Max(Simd128Register dst, Simd128Register src1,
} }
#undef F64X2_MIN_MAX_NAN #undef F64X2_MIN_MAX_NAN
void TurboAssembler::F64x2Lt(Simd128Register dst, Simd128Register src1,
Simd128Register src2) {
xvcmpgtdp(dst, src2, src1);
}
void TurboAssembler::F64x2Le(Simd128Register dst, Simd128Register src1,
Simd128Register src2) {
xvcmpgedp(dst, src2, src1);
}
void TurboAssembler::F64x2Ne(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch) {
xvcmpeqdp(scratch, src1, src2);
vnor(dst, scratch, scratch);
}
void TurboAssembler::F32x4Lt(Simd128Register dst, Simd128Register src1,
Simd128Register src2) {
xvcmpgtsp(dst, src2, src1);
}
void TurboAssembler::F32x4Le(Simd128Register dst, Simd128Register src1,
Simd128Register src2) {
xvcmpgesp(dst, src2, src1);
}
void TurboAssembler::F32x4Ne(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch) {
xvcmpeqsp(scratch, src1, src2);
vnor(dst, scratch, scratch);
}
void TurboAssembler::I64x2Ne(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch) {
vcmpequd(scratch, src1, src2);
vnor(dst, scratch, scratch);
}
void TurboAssembler::I64x2GeS(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch) {
vcmpgtsd(scratch, src2, src1);
vnor(dst, scratch, scratch);
}
void TurboAssembler::I32x4Ne(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch) {
vcmpequw(scratch, src1, src2);
vnor(dst, scratch, scratch);
}
void TurboAssembler::I32x4GeS(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch) {
vcmpgtsw(scratch, src2, src1);
vnor(dst, scratch, scratch);
}
void TurboAssembler::I32x4GeU(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch) {
vcmpequw(scratch, src1, src2);
vcmpgtuw(dst, src1, src2);
vor(dst, dst, scratch);
}
void TurboAssembler::I16x8Ne(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch) {
vcmpequh(scratch, src1, src2);
vnor(dst, scratch, scratch);
}
void TurboAssembler::I16x8GeS(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch) {
vcmpgtsh(scratch, src2, src1);
vnor(dst, scratch, scratch);
}
void TurboAssembler::I16x8GeU(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch) {
vcmpequh(scratch, src1, src2);
vcmpgtuh(dst, src1, src2);
vor(dst, dst, scratch);
}
void TurboAssembler::I8x16Ne(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch) {
vcmpequb(scratch, src1, src2);
vnor(dst, scratch, scratch);
}
void TurboAssembler::I8x16GeS(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch) {
vcmpgtsb(scratch, src2, src1);
vnor(dst, scratch, scratch);
}
void TurboAssembler::I8x16GeU(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register scratch) {
vcmpequb(scratch, src1, src2);
vcmpgtub(dst, src1, src2);
vor(dst, dst, scratch);
}
Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3,
Register reg4, Register reg5, Register reg4, Register reg5,
Register reg6) { Register reg6) {
......
src/codegen/ppc/macro-assembler-ppc.h
View file @ 429f959f
...@@ -1085,14 +1085,22 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { ...@@ -1085,14 +1085,22 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
V(F64x2Sub) \ V(F64x2Sub) \
V(F64x2Mul) \ V(F64x2Mul) \
V(F64x2Div) \ V(F64x2Div) \
V(F64x2Eq) \
V(F64x2Lt) \
V(F64x2Le) \
V(F32x4Add) \ V(F32x4Add) \
V(F32x4Sub) \ V(F32x4Sub) \
V(F32x4Mul) \ V(F32x4Mul) \
V(F32x4Div) \ V(F32x4Div) \
V(F32x4Min) \ V(F32x4Min) \
V(F32x4Max) \ V(F32x4Max) \
V(F32x4Eq) \
V(F32x4Lt) \
V(F32x4Le) \
V(I64x2Add) \ V(I64x2Add) \
V(I64x2Sub) \ V(I64x2Sub) \
V(I64x2Eq) \
V(I64x2GtS) \
V(I32x4MinS) \ V(I32x4MinS) \
V(I32x4MinU) \ V(I32x4MinU) \
V(I32x4MaxS) \ V(I32x4MaxS) \
...@@ -1100,6 +1108,9 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { ...@@ -1100,6 +1108,9 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
V(I32x4Add) \ V(I32x4Add) \
V(I32x4Sub) \ V(I32x4Sub) \
V(I32x4Mul) \ V(I32x4Mul) \
V(I32x4Eq) \
V(I32x4GtS) \
V(I32x4GtU) \
V(I16x8Add) \ V(I16x8Add) \
V(I16x8Sub) \ V(I16x8Sub) \
V(I16x8Mul) \ V(I16x8Mul) \
...@@ -1107,12 +1118,18 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { ...@@ -1107,12 +1118,18 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
V(I16x8MinU) \ V(I16x8MinU) \
V(I16x8MaxS) \ V(I16x8MaxS) \
V(I16x8MaxU) \ V(I16x8MaxU) \
V(I16x8Eq) \
V(I16x8GtS) \
V(I16x8GtU) \
V(I8x16Add) \ V(I8x16Add) \
V(I8x16Sub) \ V(I8x16Sub) \
V(I8x16MinS) \ V(I8x16MinS) \
V(I8x16MinU) \ V(I8x16MinU) \
V(I8x16MaxS) \ V(I8x16MaxS) \
V(I8x16MaxU) V(I8x16MaxU) \
V(I8x16Eq) \
V(I8x16GtS) \
V(I8x16GtU)
#define PROTOTYPE_SIMD_BINOP(name) \ #define PROTOTYPE_SIMD_BINOP(name) \
void name(Simd128Register dst, Simd128Register src1, Simd128Register src2); void name(Simd128Register dst, Simd128Register src1, Simd128Register src2);
...@@ -1179,6 +1196,32 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { ...@@ -1179,6 +1196,32 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
Simd128Register scratch1, Simd128Register scratch2); Simd128Register scratch1, Simd128Register scratch2);
void F64x2Max(Simd128Register dst, Simd128Register src1, Simd128Register src2, void F64x2Max(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch1, Simd128Register scratch2); Simd128Register scratch1, Simd128Register scratch2);
void F64x2Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void F32x4Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I64x2Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I64x2GeS(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I32x4Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I32x4GeS(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I32x4GeU(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I16x8Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I16x8GeS(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I16x8GeU(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I8x16Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I8x16GeS(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I8x16GeU(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
private: private:
static const int kSmiShift = kSmiTagSize + kSmiShiftSize; static const int kSmiShift = kSmiTagSize + kSmiShiftSize;
......
src/compiler/backend/ppc/code-generator-ppc.cc
View file @ 429f959f
...@@ -2199,14 +2199,22 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2199,14 +2199,22 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
V(F64x2Sub) \ V(F64x2Sub) \
V(F64x2Mul) \ V(F64x2Mul) \
V(F64x2Div) \ V(F64x2Div) \
V(F64x2Eq) \
V(F64x2Lt) \
V(F64x2Le) \
V(F32x4Add) \ V(F32x4Add) \
V(F32x4Sub) \ V(F32x4Sub) \
V(F32x4Mul) \ V(F32x4Mul) \
V(F32x4Div) \ V(F32x4Div) \
V(F32x4Min) \ V(F32x4Min) \
V(F32x4Max) \ V(F32x4Max) \
V(F32x4Eq) \
V(F32x4Lt) \
V(F32x4Le) \
V(I64x2Add) \ V(I64x2Add) \
V(I64x2Sub) \ V(I64x2Sub) \
V(I64x2Eq) \
V(I64x2GtS) \
V(I32x4Add) \ V(I32x4Add) \
V(I32x4Sub) \ V(I32x4Sub) \
V(I32x4Mul) \ V(I32x4Mul) \
...@@ -2214,6 +2222,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2214,6 +2222,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
V(I32x4MinU) \ V(I32x4MinU) \
V(I32x4MaxS) \ V(I32x4MaxS) \
V(I32x4MaxU) \ V(I32x4MaxU) \
V(I32x4Eq) \
V(I32x4GtS) \
V(I32x4GtU) \
V(I16x8Add) \ V(I16x8Add) \
V(I16x8Sub) \ V(I16x8Sub) \
V(I16x8Mul) \ V(I16x8Mul) \
...@@ -2221,12 +2232,18 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2221,12 +2232,18 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
V(I16x8MinU) \ V(I16x8MinU) \
V(I16x8MaxS) \ V(I16x8MaxS) \
V(I16x8MaxU) \ V(I16x8MaxU) \
V(I16x8Eq) \
V(I16x8GtS) \
V(I16x8GtU) \
V(I8x16Add) \ V(I8x16Add) \
V(I8x16Sub) \ V(I8x16Sub) \
V(I8x16MinS) \ V(I8x16MinS) \
V(I8x16MinU) \ V(I8x16MinU) \
V(I8x16MaxS) \ V(I8x16MaxS) \
V(I8x16MaxU) V(I8x16MaxU) \
V(I8x16Eq) \
V(I8x16GtS) \
V(I8x16GtU)
#define EMIT_SIMD_BINOP(name) \ #define EMIT_SIMD_BINOP(name) \
case kPPC_##name: { \ case kPPC_##name: { \
...@@ -2364,187 +2381,69 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2364,187 +2381,69 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
kScratchSimd128Reg2); kScratchSimd128Reg2);
break; break;
} }
case kPPC_F64x2Eq: {
__ xvcmpeqdp(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_F64x2Ne: { case kPPC_F64x2Ne: {
__ xvcmpeqdp(kScratchSimd128Reg, i.InputSimd128Register(0), __ F64x2Ne(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1), kScratchSimd128Reg);
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
kScratchSimd128Reg);
break;
}
case kPPC_F64x2Le: {
__ xvcmpgedp(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kPPC_F64x2Lt: {
__ xvcmpgtdp(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kPPC_F32x4Eq: {
__ xvcmpeqsp(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I64x2Eq: {
__ vcmpequd(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I32x4Eq: {
__ vcmpequw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I16x8Eq: {
__ vcmpequh(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I8x16Eq: {
__ vcmpequb(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break; break;
} }
case kPPC_F32x4Ne: { case kPPC_F32x4Ne: {
__ xvcmpeqsp(kScratchSimd128Reg, i.InputSimd128Register(0), __ F32x4Ne(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1), kScratchSimd128Reg);
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
kScratchSimd128Reg);
break; break;
} }
case kPPC_I64x2Ne: { case kPPC_I64x2Ne: {
__ vcmpequd(kScratchSimd128Reg, i.InputSimd128Register(0), __ I64x2Ne(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1), kScratchSimd128Reg);
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
kScratchSimd128Reg);
break;
}
case kPPC_I32x4Ne: {
__ vcmpequw(kScratchSimd128Reg, i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
kScratchSimd128Reg);
break;
}
case kPPC_I16x8Ne: {
__ vcmpequh(kScratchSimd128Reg, i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
kScratchSimd128Reg);
break;
}
case kPPC_I8x16Ne: {
__ vcmpequb(kScratchSimd128Reg, i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
kScratchSimd128Reg);
break;
}
case kPPC_F32x4Lt: {
__ xvcmpgtsp(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kPPC_F32x4Le: {
__ xvcmpgesp(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kPPC_I64x2GtS: {
__ vcmpgtsd(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I32x4GtS: {
__ vcmpgtsw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break; break;
} }
case kPPC_I64x2GeS: { case kPPC_I64x2GeS: {
__ vcmpgtsd(kScratchSimd128Reg, i.InputSimd128Register(1), __ I64x2GeS(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(0)); i.InputSimd128Register(1), kScratchSimd128Reg);
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
kScratchSimd128Reg);
break; break;
} }
case kPPC_I32x4GeS: { case kPPC_I32x4Ne: {
__ vcmpgtsw(kScratchSimd128Reg, i.InputSimd128Register(1), __ I32x4Ne(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(0)); i.InputSimd128Register(1), kScratchSimd128Reg);
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
kScratchSimd128Reg);
break; break;
} }
case kPPC_I32x4GtU: { case kPPC_I32x4GeS: {
__ vcmpgtuw(i.OutputSimd128Register(), i.InputSimd128Register(0), __ I32x4GeS(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1), kScratchSimd128Reg);
break; break;
} }
case kPPC_I32x4GeU: { case kPPC_I32x4GeU: {
__ vcmpequw(kScratchSimd128Reg, i.InputSimd128Register(0), __ I32x4GeU(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1), kScratchSimd128Reg);
__ vcmpgtuw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
kScratchSimd128Reg);
break; break;
} }
case kPPC_I16x8GtS: { case kPPC_I16x8Ne: {
__ vcmpgtsh(i.OutputSimd128Register(), i.InputSimd128Register(0), __ I16x8Ne(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1), kScratchSimd128Reg);
break; break;
} }
case kPPC_I16x8GeS: { case kPPC_I16x8GeS: {
__ vcmpgtsh(kScratchSimd128Reg, i.InputSimd128Register(1), __ I16x8GeS(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(0)); i.InputSimd128Register(1), kScratchSimd128Reg);
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
kScratchSimd128Reg);
break;
}
case kPPC_I16x8GtU: {
__ vcmpgtuh(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break; break;
} }
case kPPC_I16x8GeU: { case kPPC_I16x8GeU: {
__ vcmpequh(kScratchSimd128Reg, i.InputSimd128Register(0), __ I16x8GeU(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1), kScratchSimd128Reg);
__ vcmpgtuh(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
kScratchSimd128Reg);
break; break;
} }
case kPPC_I8x16GtS: { case kPPC_I8x16Ne: {
__ vcmpgtsb(i.OutputSimd128Register(), i.InputSimd128Register(0), __ I8x16Ne(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1), kScratchSimd128Reg);
break; break;
} }
case kPPC_I8x16GeS: { case kPPC_I8x16GeS: {
__ vcmpgtsb(kScratchSimd128Reg, i.InputSimd128Register(1), __ I8x16GeS(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(0)); i.InputSimd128Register(1), kScratchSimd128Reg);
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
kScratchSimd128Reg);
break;
}
case kPPC_I8x16GtU: {
__ vcmpgtub(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break; break;
} }
case kPPC_I8x16GeU: { case kPPC_I8x16GeU: {
__ vcmpequb(kScratchSimd128Reg, i.InputSimd128Register(0), __ I8x16GeU(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1), kScratchSimd128Reg);
__ vcmpgtub(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
kScratchSimd128Reg);
break; break;
} }
#define VECTOR_SHIFT(op) \ #define VECTOR_SHIFT(op) \
......
src/wasm/baseline/ppc/liftoff-assembler-ppc.h
View file @ 429f959f
...@@ -1774,14 +1774,22 @@ bool LiftoffAssembler::emit_select(LiftoffRegister dst, Register condition, ...@@ -1774,14 +1774,22 @@ bool LiftoffAssembler::emit_select(LiftoffRegister dst, Register condition,
V(f64x2_sub, F64x2Sub) \ V(f64x2_sub, F64x2Sub) \
V(f64x2_mul, F64x2Mul) \ V(f64x2_mul, F64x2Mul) \
V(f64x2_div, F64x2Div) \ V(f64x2_div, F64x2Div) \
V(f64x2_eq, F64x2Eq) \
V(f64x2_lt, F64x2Lt) \
V(f64x2_le, F64x2Le) \
V(f32x4_add, F32x4Add) \ V(f32x4_add, F32x4Add) \
V(f32x4_sub, F32x4Sub) \ V(f32x4_sub, F32x4Sub) \
V(f32x4_mul, F32x4Mul) \ V(f32x4_mul, F32x4Mul) \
V(f32x4_div, F32x4Div) \ V(f32x4_div, F32x4Div) \
V(f32x4_min, F32x4Min) \ V(f32x4_min, F32x4Min) \
V(f32x4_max, F32x4Max) \ V(f32x4_max, F32x4Max) \
V(f32x4_eq, F32x4Eq) \
V(f32x4_lt, F32x4Lt) \
V(f32x4_le, F32x4Le) \
V(i64x2_add, I64x2Add) \ V(i64x2_add, I64x2Add) \
V(i64x2_sub, I64x2Sub) \ V(i64x2_sub, I64x2Sub) \
V(i64x2_eq, I64x2Eq) \
V(i64x2_gt_s, I64x2GtS) \
V(i32x4_add, I32x4Add) \ V(i32x4_add, I32x4Add) \
V(i32x4_sub, I32x4Sub) \ V(i32x4_sub, I32x4Sub) \
V(i32x4_mul, I32x4Mul) \ V(i32x4_mul, I32x4Mul) \
...@@ -1789,6 +1797,9 @@ bool LiftoffAssembler::emit_select(LiftoffRegister dst, Register condition, ...@@ -1789,6 +1797,9 @@ bool LiftoffAssembler::emit_select(LiftoffRegister dst, Register condition,
V(i32x4_min_u, I32x4MinU) \ V(i32x4_min_u, I32x4MinU) \
V(i32x4_max_s, I32x4MaxS) \ V(i32x4_max_s, I32x4MaxS) \
V(i32x4_max_u, I32x4MaxU) \ V(i32x4_max_u, I32x4MaxU) \
V(i32x4_eq, I32x4Eq) \
V(i32x4_gt_s, I32x4GtS) \
V(i32x4_gt_u, I32x4GtU) \
V(i16x8_add, I16x8Add) \ V(i16x8_add, I16x8Add) \
V(i16x8_sub, I16x8Sub) \ V(i16x8_sub, I16x8Sub) \
V(i16x8_mul, I16x8Mul) \ V(i16x8_mul, I16x8Mul) \
...@@ -1796,12 +1807,18 @@ bool LiftoffAssembler::emit_select(LiftoffRegister dst, Register condition, ...@@ -1796,12 +1807,18 @@ bool LiftoffAssembler::emit_select(LiftoffRegister dst, Register condition,
V(i16x8_min_u, I16x8MinU) \ V(i16x8_min_u, I16x8MinU) \
V(i16x8_max_s, I16x8MaxS) \ V(i16x8_max_s, I16x8MaxS) \
V(i16x8_max_u, I16x8MaxU) \ V(i16x8_max_u, I16x8MaxU) \
V(i16x8_eq, I16x8Eq) \
V(i16x8_gt_s, I16x8GtS) \
V(i16x8_gt_u, I16x8GtU) \
V(i8x16_add, I8x16Add) \ V(i8x16_add, I8x16Add) \
V(i8x16_sub, I8x16Sub) \ V(i8x16_sub, I8x16Sub) \
V(i8x16_min_s, I8x16MinS) \ V(i8x16_min_s, I8x16MinS) \
V(i8x16_min_u, I8x16MinU) \ V(i8x16_min_u, I8x16MinU) \
V(i8x16_max_s, I8x16MaxS) \ V(i8x16_max_s, I8x16MaxS) \
V(i8x16_max_u, I8x16MaxU) V(i8x16_max_u, I8x16MaxU) \
V(i8x16_eq, I8x16Eq) \
V(i8x16_gt_s, I8x16GtS) \
V(i8x16_gt_u, I8x16GtU)
#define EMIT_SIMD_BINOP(name, op) \ #define EMIT_SIMD_BINOP(name, op) \
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \ void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
...@@ -1968,6 +1985,84 @@ void LiftoffAssembler::emit_f64x2_max(LiftoffRegister dst, LiftoffRegister lhs, ...@@ -1968,6 +1985,84 @@ void LiftoffAssembler::emit_f64x2_max(LiftoffRegister dst, LiftoffRegister lhs,
kScratchSimd128Reg, kScratchSimd128Reg2); kScratchSimd128Reg, kScratchSimd128Reg2);
} }
void LiftoffAssembler::emit_f64x2_ne(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
F64x2Ne(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
kScratchSimd128Reg);
}
void LiftoffAssembler::emit_f32x4_ne(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
F32x4Ne(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i64x2_ne(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I64x2Ne(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i64x2_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I64x2GeS(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i32x4_ne(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I32x4Ne(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i32x4_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I32x4GeS(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i32x4_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I32x4GeU(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i16x8_ne(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I16x8Ne(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i16x8_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I16x8GeS(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i16x8_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I16x8GeU(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i8x16_ne(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I8x16Ne(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i8x16_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I8x16GeS(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i8x16_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
I8x16GeU(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
kScratchSimd128Reg);
}
void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr, void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr,
Register offset_reg, uintptr_t offset_imm, Register offset_reg, uintptr_t offset_imm,
LoadType type, LoadType type,
...@@ -2553,156 +2648,6 @@ void LiftoffAssembler::emit_i8x16_add_sat_s(LiftoffRegister dst, ...@@ -2553,156 +2648,6 @@ void LiftoffAssembler::emit_i8x16_add_sat_s(LiftoffRegister dst,
bailout(kUnsupportedArchitecture, "emit_i8x16addsaturate_s"); bailout(kUnsupportedArchitecture, "emit_i8x16addsaturate_s");
} }
void LiftoffAssembler::emit_i8x16_eq(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i8x16_eq");
}
void LiftoffAssembler::emit_i8x16_ne(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i8x16_ne");
}
void LiftoffAssembler::emit_i8x16_gt_s(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i8x16gt_s");
}
void LiftoffAssembler::emit_i8x16_gt_u(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i8x16gt_u");
}
void LiftoffAssembler::emit_i8x16_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i8x16ge_s");
}
void LiftoffAssembler::emit_i8x16_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i8x16ge_u");
}
void LiftoffAssembler::emit_i16x8_eq(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i16x8_eq");
}
void LiftoffAssembler::emit_i16x8_ne(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i16x8_ne");
}
void LiftoffAssembler::emit_i16x8_gt_s(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i16x8gt_s");
}
void LiftoffAssembler::emit_i16x8_gt_u(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i16x8gt_u");
}
void LiftoffAssembler::emit_i16x8_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i16x8ge_s");
}
void LiftoffAssembler::emit_i16x8_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i16x8ge_u");
}
void LiftoffAssembler::emit_i32x4_eq(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i32x4_eq");
}
void LiftoffAssembler::emit_i32x4_ne(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i32x4_ne");
}
void LiftoffAssembler::emit_i32x4_gt_s(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i32x4gt_s");
}
void LiftoffAssembler::emit_i32x4_gt_u(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_32x4gt_u");
}
void LiftoffAssembler::emit_i32x4_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i32x4ge_s");
}
void LiftoffAssembler::emit_i32x4_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i32x4ge_u");
}
void LiftoffAssembler::emit_i64x2_eq(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "i64x2.eq");
}
void LiftoffAssembler::emit_i64x2_ne(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "i64x2_ne");
}
void LiftoffAssembler::emit_i64x2_gt_s(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "i64x2.gt_s");
}
void LiftoffAssembler::emit_i64x2_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "i64x2.ge_s");
}
void LiftoffAssembler::emit_f32x4_eq(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f32x4_eq");
}
void LiftoffAssembler::emit_f32x4_ne(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f32x4_ne");
}
void LiftoffAssembler::emit_f32x4_lt(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f32x4_lt");
}
void LiftoffAssembler::emit_f32x4_le(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f32x4_le");
}
void LiftoffAssembler::emit_f64x2_eq(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f64x2_eq");
}
void LiftoffAssembler::emit_f64x2_ne(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f64x2_ne");
}
void LiftoffAssembler::emit_f64x2_lt(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f64x2_lt");
}
void LiftoffAssembler::emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f64x2_le");
}
void LiftoffAssembler::emit_s128_const(LiftoffRegister dst, void LiftoffAssembler::emit_s128_const(LiftoffRegister dst,
const uint8_t imms[16]) { const uint8_t imms[16]) {
bailout(kUnsupportedArchitecture, "emit_s128_const"); bailout(kUnsupportedArchitecture, "emit_s128_const");
......
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