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Commit 419eddda authored by Ilija Pavlovic's avatar Ilija Pavlovic Committed by Commit Bot
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MIPS: Use macro-instructions in code-generator. 

Port for: https://chromium-review.googlesource.com/c/v8/v8/+/608975

In code generator for MIPS32, certain instructions are substituted with
corresponding macro-instructions.

TEST=
BUG=

Change-Id: I2ac47a785f0ea14c448f727da124dc78ea6c81af
Reviewed-on: https://chromium-review.googlesource.com/699998Reviewed-by: 's avatarIvica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#48278}
parent 51334bb8
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Showing with 29 additions and 34 deletions
src/compiler/mips/code-generator-mips.cc
View file @ 419eddda
......@@ -397,7 +397,6 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
} // namespace
#define ASSEMBLE_CHECKED_LOAD_FLOAT(width, asm_instr) \
do { \
auto result = i.Output##width##Register(); \
......@@ -405,7 +404,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
if (instr->InputAt(0)->IsRegister()) { \
auto offset = i.InputRegister(0); \
__ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \
__ addu(kScratchReg, i.InputRegister(2), offset); \
__ Addu(kScratchReg, i.InputRegister(2), offset); \
__ asm_instr(result, MemOperand(kScratchReg, 0)); \
} else { \
auto offset = i.InputOperand(0).immediate(); \
......@@ -415,7 +414,6 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
__ bind(ool->exit()); \
} while (0)
#define ASSEMBLE_CHECKED_LOAD_INTEGER(asm_instr) \
do { \
auto result = i.OutputRegister(); \
......@@ -423,7 +421,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
if (instr->InputAt(0)->IsRegister()) { \
auto offset = i.InputRegister(0); \
__ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \
__ addu(kScratchReg, i.InputRegister(2), offset); \
__ Addu(kScratchReg, i.InputRegister(2), offset); \
__ asm_instr(result, MemOperand(kScratchReg, 0)); \
} else { \
auto offset = i.InputOperand(0).immediate(); \
......@@ -443,7 +441,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
__ Move(kDoubleRegZero, 0.0); \
} \
__ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
__ addu(kScratchReg, i.InputRegister(3), offset); \
__ Addu(kScratchReg, i.InputRegister(3), offset); \
__ asm_instr(value, MemOperand(kScratchReg, 0)); \
} else { \
auto offset = i.InputOperand(0).immediate(); \
......@@ -464,7 +462,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
auto offset = i.InputRegister(0); \
auto value = i.InputOrZeroRegister(2); \
__ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
__ addu(kScratchReg, i.InputRegister(3), offset); \
__ Addu(kScratchReg, i.InputRegister(3), offset); \
__ asm_instr(value, MemOperand(kScratchReg, 0)); \
} else { \
auto offset = i.InputOperand(0).immediate(); \
......@@ -543,7 +541,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
#define ASSEMBLE_ATOMIC_BINOP(bin_instr) \
do { \
Label binop; \
__ addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ Addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ sync(); \
__ bind(&binop); \
__ Ll(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0)); \
......@@ -557,7 +555,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
#define ASSEMBLE_ATOMIC_BINOP_EXT(sign_extend, size, bin_instr) \
do { \
Label binop; \
__ addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ Addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ andi(i.TempRegister(3), i.TempRegister(0), 0x3); \
__ Subu(i.TempRegister(0), i.TempRegister(0), Operand(i.TempRegister(3))); \
__ sll(i.TempRegister(3), i.TempRegister(3), 3); \
......@@ -580,7 +578,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
Label exchange; \
__ sync(); \
__ bind(&exchange); \
__ addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ Addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ Ll(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0)); \
__ mov(i.TempRegister(1), i.InputRegister(2)); \
__ Sc(i.TempRegister(1), MemOperand(i.TempRegister(0), 0)); \
......@@ -591,7 +589,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT(sign_extend, size) \
do { \
Label exchange; \
__ addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ Addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ andi(i.TempRegister(1), i.TempRegister(0), 0x3); \
__ Subu(i.TempRegister(0), i.TempRegister(0), Operand(i.TempRegister(1))); \
__ sll(i.TempRegister(1), i.TempRegister(1), 3); \
......@@ -611,7 +609,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
do { \
Label compareExchange; \
Label exit; \
__ addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ Addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ sync(); \
__ bind(&compareExchange); \
__ Ll(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0)); \
......@@ -629,7 +627,7 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
do { \
Label compareExchange; \
Label exit; \
__ addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ Addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ andi(i.TempRegister(1), i.TempRegister(0), 0x3); \
__ Subu(i.TempRegister(0), i.TempRegister(0), Operand(i.TempRegister(1))); \
__ sll(i.TempRegister(1), i.TempRegister(1), 3); \
......@@ -1140,7 +1138,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
// We don't have an instruction to count the number of trailing zeroes.
// Start by flipping the bits end-for-end so we can count the number of
// leading zeroes instead.
__ rotr(dst, src, 16);
__ Ror(dst, src, 16);
__ wsbh(dst, dst);
__ bitswap(dst, dst);
__ Clz(dst, dst);
......@@ -1363,8 +1361,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kMipsMulPair: {
__ Mulu(i.OutputRegister(1), i.OutputRegister(0), i.InputRegister(0),
i.InputRegister(2));
__ mul(kScratchReg, i.InputRegister(0), i.InputRegister(3));
__ mul(kScratchReg2, i.InputRegister(1), i.InputRegister(2));
__ Mul(kScratchReg, i.InputRegister(0), i.InputRegister(3));
__ Mul(kScratchReg2, i.InputRegister(1), i.InputRegister(2));
__ Addu(i.OutputRegister(1), i.OutputRegister(1), kScratchReg);
__ Addu(i.OutputRegister(1), i.OutputRegister(1), kScratchReg2);
} break;
......@@ -1541,26 +1539,26 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMipsFloorWD: {
FPURegister scratch = kScratchDoubleReg;
__ floor_w_d(scratch, i.InputDoubleRegister(0));
__ Floor_w_d(scratch, i.InputDoubleRegister(0));
__ mfc1(i.OutputRegister(), scratch);
break;
}
case kMipsCeilWD: {
FPURegister scratch = kScratchDoubleReg;
__ ceil_w_d(scratch, i.InputDoubleRegister(0));
__ Ceil_w_d(scratch, i.InputDoubleRegister(0));
__ mfc1(i.OutputRegister(), scratch);
break;
}
case kMipsRoundWD: {
FPURegister scratch = kScratchDoubleReg;
__ round_w_d(scratch, i.InputDoubleRegister(0));
__ Round_w_d(scratch, i.InputDoubleRegister(0));
__ mfc1(i.OutputRegister(), scratch);
break;
}
case kMipsTruncWD: {
FPURegister scratch = kScratchDoubleReg;
// Other arches use round to zero here, so we follow.
__ trunc_w_d(scratch, i.InputDoubleRegister(0));
__ Trunc_w_d(scratch, i.InputDoubleRegister(0));
__ mfc1(i.OutputRegister(), scratch);
break;
}
......@@ -1588,8 +1586,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ mfc1(i.OutputRegister(), scratch);
// Avoid INT32_MAX as an overflow indicator and use INT32_MIN instead,
// because INT32_MIN allows easier out-of-bounds detection.
__ addiu(kScratchReg, i.OutputRegister(), 1);
__ slt(kScratchReg2, kScratchReg, i.OutputRegister());
__ Addu(kScratchReg, i.OutputRegister(), 1);
__ Slt(kScratchReg2, kScratchReg, i.OutputRegister());
__ Movn(i.OutputRegister(), kScratchReg, kScratchReg2);
break;
}
......@@ -1605,7 +1603,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ Trunc_uw_s(i.InputDoubleRegister(0), i.OutputRegister(), scratch);
// Avoid UINT32_MAX as an overflow indicator and use 0 instead,
// because 0 allows easier out-of-bounds detection.
__ addiu(kScratchReg, i.OutputRegister(), 1);
__ Addu(kScratchReg, i.OutputRegister(), 1);
__ Movz(i.OutputRegister(), zero_reg, kScratchReg);
break;
}
......
src/mips/macro-assembler-mips.cc
View file @ 419eddda
......@@ -1861,7 +1861,7 @@ void TurboAssembler::Trunc_uw_s(FPURegister fd, FPURegister fs,
mtc1(t8, fd);
}
void MacroAssembler::Trunc_w_d(FPURegister fd, FPURegister fs) {
void TurboAssembler::Trunc_w_d(FPURegister fd, FPURegister fs) {
if (IsMipsArchVariant(kLoongson) && fd == fs) {
Mfhc1(t8, fs);
trunc_w_d(fd, fs);
......@@ -1871,8 +1871,7 @@ void MacroAssembler::Trunc_w_d(FPURegister fd, FPURegister fs) {
}
}
void MacroAssembler::Round_w_d(FPURegister fd, FPURegister fs) {
void TurboAssembler::Round_w_d(FPURegister fd, FPURegister fs) {
if (IsMipsArchVariant(kLoongson) && fd == fs) {
Mfhc1(t8, fs);
round_w_d(fd, fs);
......@@ -1882,8 +1881,7 @@ void MacroAssembler::Round_w_d(FPURegister fd, FPURegister fs) {
}
}
void MacroAssembler::Floor_w_d(FPURegister fd, FPURegister fs) {
void TurboAssembler::Floor_w_d(FPURegister fd, FPURegister fs) {
if (IsMipsArchVariant(kLoongson) && fd == fs) {
Mfhc1(t8, fs);
floor_w_d(fd, fs);
......@@ -1893,8 +1891,7 @@ void MacroAssembler::Floor_w_d(FPURegister fd, FPURegister fs) {
}
}
void MacroAssembler::Ceil_w_d(FPURegister fd, FPURegister fs) {
void TurboAssembler::Ceil_w_d(FPURegister fd, FPURegister fs) {
if (IsMipsArchVariant(kLoongson) && fd == fs) {
Mfhc1(t8, fs);
ceil_w_d(fd, fs);
......
src/mips/macro-assembler-mips.h
View file @ 419eddda
......@@ -609,6 +609,11 @@ class TurboAssembler : public Assembler {
void Trunc_uw_s(FPURegister fd, FPURegister fs, FPURegister scratch);
void Trunc_uw_s(FPURegister fd, Register rs, FPURegister scratch);
void Trunc_w_d(FPURegister fd, FPURegister fs);
void Round_w_d(FPURegister fd, FPURegister fs);
void Floor_w_d(FPURegister fd, FPURegister fs);
void Ceil_w_d(FPURegister fd, FPURegister fs);
// FP32 mode: Move the general purpose register into
// the high part of the double-register pair.
// FP64 mode: Move the general-purpose register into
......@@ -1057,11 +1062,6 @@ class MacroAssembler : public TurboAssembler {
void PushSafepointRegisters();
void PopSafepointRegisters();
void Trunc_w_d(FPURegister fd, FPURegister fs);
void Round_w_d(FPURegister fd, FPURegister fs);
void Floor_w_d(FPURegister fd, FPURegister fs);
void Ceil_w_d(FPURegister fd, FPURegister fs);
// Truncates a double using a specific rounding mode, and writes the value
// to the result register.
// The except_flag will contain any exceptions caused by the instruction.
......
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