Commit 3e40d280 authored by Junliang Yan's avatar Junliang Yan Committed by Commit Bot

s390x: [liftoff][arm] Make context register allocatable

Port 4b3371c6

Original Message:
  This will make it easier to generate builtin calls that require the
  context to be passed in that register, because this can be represented
  as a {LiftoffRegister} then.

Change-Id: I35f14d9f5460706ef1d51f39a7eb3afdf0979f9d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2764682Reviewed-by: 's avatarMilad Fa <mfarazma@redhat.com>
Reviewed-by: 's avatarClemens Backes <clemensb@chromium.org>
Commit-Queue: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#73543}
parent 81008e17
...@@ -47,7 +47,7 @@ class WasmCompileLazyFrameConstants : public TypedFrameConstants { ...@@ -47,7 +47,7 @@ class WasmCompileLazyFrameConstants : public TypedFrameConstants {
class WasmDebugBreakFrameConstants : public TypedFrameConstants { class WasmDebugBreakFrameConstants : public TypedFrameConstants {
public: public:
static constexpr RegList kPushedGpRegs = static constexpr RegList kPushedGpRegs =
Register::ListOf(r2, r3, r4, r5, r6, r7, r8); Register::ListOf(r2, r3, r4, r5, r6, r7, r8, cp);
static constexpr RegList kPushedFpRegs = DoubleRegister::ListOf( static constexpr RegList kPushedFpRegs = DoubleRegister::ListOf(
d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12); d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12);
......
...@@ -72,7 +72,7 @@ constexpr RegList kLiftoffAssemblerFpCacheRegs = CPURegister::ListOf( ...@@ -72,7 +72,7 @@ constexpr RegList kLiftoffAssemblerFpCacheRegs = CPURegister::ListOf(
#elif V8_TARGET_ARCH_S390X #elif V8_TARGET_ARCH_S390X
constexpr RegList kLiftoffAssemblerGpCacheRegs = constexpr RegList kLiftoffAssemblerGpCacheRegs =
Register::ListOf(r2, r3, r4, r5, r6, r7, r8); Register::ListOf(r2, r3, r4, r5, r6, r7, r8, cp);
constexpr RegList kLiftoffAssemblerFpCacheRegs = DoubleRegister::ListOf( constexpr RegList kLiftoffAssemblerFpCacheRegs = DoubleRegister::ListOf(
d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12); d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12);
......
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