[riscv64] Add macro to control disassemble rvv

Change-Id: Iad4b34b1c4a85800e8e1d6c01b686dd19e8116a6
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3600532
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Commit-Queue: ji qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#80508}

src/codegen/riscv64/assembler-riscv64.cc

@@ -59,7 +59,7 @@ static unsigned CpuFeaturesImpliedByCompiler() {
 
 #if (defined CAN_USE_RVV_INSTRUCTIONS)
   answer |= 1u << RISCV_SIMD;
-#endif  // def CAN_USE_RVV_INSTRUCTIONS || USE_SIMULATOR
+#endif  // def CAN_USE_RVV_INSTRUCTIONS
   return answer;
 }
 
@@ -2913,6 +2913,7 @@ uint8_t vsew_switch(VSew vsew) {
 
 void Assembler::vl(VRegister vd, Register rs1, uint8_t lumop, VSew vsew,
                    MaskType mask) {
+  std::cout << "vl" << std::endl;
   uint8_t width = vsew_switch(vsew);
   GenInstrV(LOAD_FP, width, vd, rs1, lumop, mask, 0b00, 0, 0b000);
 }

src/diagnostics/riscv64/disasm-riscv64.cc

@@ -1412,16 +1412,12 @@ void Decoder::DecodeR4Type(Instruction* instr) {
 }
 
 void Decoder::DecodeIType(Instruction* instr) {
-  if (instr->vl_vs_width() != -1) {
-    DecodeRvvVL(instr);
-  } else {
   switch (instr->InstructionBits() & kITypeMask) {
     case RO_JALR:
       if (instr->RdValue() == zero_reg.code() &&
           instr->Rs1Value() == ra.code() && instr->Imm12Value() == 0)
         Format(instr, "ret");
-        else if (instr->RdValue() == zero_reg.code() &&
-                 instr->Imm12Value() == 0)
+      else if (instr->RdValue() == zero_reg.code() && instr->Imm12Value() == 0)
         Format(instr, "jr        'rs1");
       else if (instr->RdValue() == ra.code() && instr->Imm12Value() == 0)
         Format(instr, "jalr      'rs1");
@@ -1634,15 +1630,18 @@ void Decoder::DecodeIType(Instruction* instr) {
       Format(instr, "fld       'fd, 'imm12('rs1)");
       break;
     default:
+#ifdef CAN_USE_RVV_INSTRUCTIONS
+      if (!DecodeRvvVL()) {
         UNSUPPORTED_RISCV();
       }
+      break;
+#else
+      UNSUPPORTED_RISCV();
+#endif
   }
 }
 
 void Decoder::DecodeSType(Instruction* instr) {
-  if (instr->vl_vs_width() != -1) {
-    DecodeRvvVS(instr);
-  } else {
   switch (instr->InstructionBits() & kSTypeMask) {
     case RO_SB:
       Format(instr, "sb        'rs2, 'offS('rs1)");
@@ -1667,10 +1666,17 @@ void Decoder::DecodeSType(Instruction* instr) {
       Format(instr, "fsd       'fs2, 'offS('rs1)");
       break;
     default:
+#ifdef CAN_USE_RVV_INSTRUCTIONS
+      if (!DecodeRvvVS()) {
         UNSUPPORTED_RISCV();
       }
+      break;
+#else
+      UNSUPPORTED_RISCV();
+#endif
   }
 }
+
 void Decoder::DecodeBType(Instruction* instr) {
   switch (instr->InstructionBits() & kBTypeMask) {
     case RO_BEQ:
@@ -2867,9 +2873,11 @@ int Decoder::InstructionDecode(byte* instr_ptr) {
     case Instruction::kCBType:
       DecodeCBType(instr);
       break;
+#ifdef CAN_USE_RVV_INSTRUCTIONS
     case Instruction::kVType:
       DecodeVType(instr);
       break;
+#endif
     default:
       Format(instr, "UNSUPPORTED");
       UNSUPPORTED_RISCV();

src/execution/riscv64/simulator-riscv64.cc

@@ -88,6 +88,7 @@
 // PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
 // HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
 // MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
+#ifdef CAN_USE_RVV_INSTRUCTIONS
 static inline bool is_aligned(const unsigned val, const unsigned pos) {
   return pos ? (val & (pos - 1)) == 0 : true;
 }
@@ -155,7 +156,6 @@ static inline bool is_overlapped_widen(const int astart, int asize,
 // PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
 // HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
 // MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
-#ifdef CAN_USE_RVV_INSTRUCTIONS
 template <uint64_t N>
 struct type_usew_t;
 template <>
@@ -4635,10 +4635,10 @@ void Simulator::DecodeRVIType() {
       if (!DecodeRvvVL()) {
         UNSUPPORTED();
       }
+      break;
 #else
       UNSUPPORTED();
 #endif
-      break;
     }
   }
 }
@@ -4676,10 +4676,10 @@ void Simulator::DecodeRVSType() {
       if (!DecodeRvvVS()) {
         UNSUPPORTED();
       }
+      break;
 #else
       UNSUPPORTED();
 #endif
-      break;
   }
 }