Commit 3c8c1c9d authored by Ng Zhi An's avatar Ng Zhi An Committed by Commit Bot

[wasm-simd] Clean up unused simd shift immediates

SIMD shifts was changed to use register in https://crrev.com/c/1722198
so all this code to deal with shift immediates can be removed.

SimdOp was also removed from the interface, so now Liftoff does not need
to implement it.

Bug: v8:9810
Change-Id: I845e28b4f5712ff188d68beea7121eebddebdd9e
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1913506Reviewed-by: 's avatarBill Budge <bbudge@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64944}
parent b4bfbce6
...@@ -2031,11 +2031,6 @@ class LiftoffCompiler { ...@@ -2031,11 +2031,6 @@ class LiftoffCompiler {
const Vector<Value> inputs, Value* result) { const Vector<Value> inputs, Value* result) {
unsupported(decoder, kSimd, "simd"); unsupported(decoder, kSimd, "simd");
} }
void SimdShiftOp(FullDecoder* decoder, WasmOpcode opcode,
const SimdShiftImmediate<validate>& imm, const Value& input,
Value* result) {
unsupported(decoder, kSimd, "simd");
}
void Simd8x16ShuffleOp(FullDecoder* decoder, void Simd8x16ShuffleOp(FullDecoder* decoder,
const Simd8x16ShuffleImmediate<validate>& imm, const Simd8x16ShuffleImmediate<validate>& imm,
const Value& input0, const Value& input1, const Value& input0, const Value& input1,
......
...@@ -486,17 +486,6 @@ struct SimdLaneImmediate { ...@@ -486,17 +486,6 @@ struct SimdLaneImmediate {
} }
}; };
// Immediate for SIMD shift operations.
template <Decoder::ValidateFlag validate>
struct SimdShiftImmediate {
uint8_t shift;
uint32_t length = 1;
inline SimdShiftImmediate(Decoder* decoder, const byte* pc) {
shift = decoder->read_u8<validate>(pc + 2, "shift");
}
};
// Immediate for SIMD S8x16 shuffle operations. // Immediate for SIMD S8x16 shuffle operations.
template <Decoder::ValidateFlag validate> template <Decoder::ValidateFlag validate>
struct Simd8x16ShuffleImmediate { struct Simd8x16ShuffleImmediate {
...@@ -1098,42 +1087,6 @@ class WasmDecoder : public Decoder { ...@@ -1098,42 +1087,6 @@ class WasmDecoder : public Decoder {
} }
} }
inline bool Validate(const byte* pc, WasmOpcode opcode,
SimdShiftImmediate<validate>& imm) {
uint8_t max_shift = 0;
switch (opcode) {
case kExprI64x2Shl:
case kExprI64x2ShrS:
case kExprI64x2ShrU:
max_shift = 64;
break;
case kExprI32x4Shl:
case kExprI32x4ShrS:
case kExprI32x4ShrU:
max_shift = 32;
break;
case kExprI16x8Shl:
case kExprI16x8ShrS:
case kExprI16x8ShrU:
max_shift = 16;
break;
case kExprI8x16Shl:
case kExprI8x16ShrS:
case kExprI8x16ShrU:
max_shift = 8;
break;
default:
UNREACHABLE();
break;
}
if (!VALIDATE(imm.shift >= 0 && imm.shift < max_shift)) {
error(pc_ + 2, "invalid shift amount");
return false;
} else {
return true;
}
}
inline bool Validate(const byte* pc, inline bool Validate(const byte* pc,
Simd8x16ShuffleImmediate<validate>& imm) { Simd8x16ShuffleImmediate<validate>& imm) {
uint8_t max_lane = 0; uint8_t max_lane = 0;
......
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