[loong64][mips64][compiler] Merge all CompileFoo_Bar runtime functions

Port commit 8b4272c2

Bug: v8:7700
Change-Id: I9d75fd3341e7bf7d2f0b822b7892683857050594
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3830646
Auto-Submit: Liu Yu <liuyu@loongson.cn>
Reviewed-by: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/main@{#82459}

src/codegen/loong64/macro-assembler-loong64.cc

@@ -4161,39 +4161,6 @@ void TurboAssembler::JumpCodeObject(Register code_object, JumpMode jump_mode) {
 
 namespace {
 
-// Tail-call |function_id| if |actual_state| == |expected_state|
-void TailCallRuntimeIfStateEquals(MacroAssembler* masm, Register actual_state,
-                                  TieringState expected_state,
-                                  Runtime::FunctionId function_id) {
-  ASM_CODE_COMMENT(masm);
-  Label no_match;
-  __ Branch(&no_match, ne, actual_state,
-            Operand(static_cast<int>(expected_state)));
-  __ GenerateTailCallToReturnedCode(function_id);
-  __ bind(&no_match);
-}
-
-void MaybeOptimizeCode(MacroAssembler* masm, Register tiering_state) {
-  // ----------- S t a t e -------------
-  //  -- a0 : actual argument count
-  //  -- a3 : new target (preserved for callee if needed, and caller)
-  //  -- a1 : target function (preserved for callee if needed, and caller)
-  //  -- feedback vector (preserved for caller if needed)
-  //  -- tiering_state : a Smi containing a non-zero tiering state.
-  // -----------------------------------
-  ASM_CODE_COMMENT(masm);
-  DCHECK(!AreAliased(a1, a3, tiering_state));
-
-  TailCallRuntimeIfStateEquals(masm, tiering_state,
-                               TieringState::kRequestTurbofan_Synchronous,
-                               Runtime::kCompileTurbofan_Synchronous);
-  TailCallRuntimeIfStateEquals(masm, tiering_state,
-                               TieringState::kRequestTurbofan_Concurrent,
-                               Runtime::kCompileTurbofan_Concurrent);
-
-  __ stop();
-}
-
 void TailCallOptimizedCodeSlot(MacroAssembler* masm,
                                Register optimized_code_entry) {
   // ----------- S t a t e -------------
@@ -4303,7 +4270,7 @@ void MacroAssembler::MaybeOptimizeCodeOrTailCallOptimizedCodeSlot(
   ASM_CODE_COMMENT(this);
   DCHECK(!AreAliased(optimization_state, feedback_vector));
   Label maybe_has_optimized_code;
-  // Check if optimized code marker is available
+  // Check if optimized code marker is available.
   {
     UseScratchRegisterScope temps(this);
     Register scratch = temps.Acquire();
@@ -4312,9 +4279,7 @@ void MacroAssembler::MaybeOptimizeCodeOrTailCallOptimizedCodeSlot(
     Branch(&maybe_has_optimized_code, eq, scratch, Operand(zero_reg));
   }
 
-  Register tiering_state = optimization_state;
-  DecodeField<FeedbackVector::TieringStateBits>(tiering_state);
-  MaybeOptimizeCode(this, tiering_state);
+  GenerateTailCallToReturnedCode(Runtime::kCompileOptimized);
 
   bind(&maybe_has_optimized_code);
   Register optimized_code_entry = optimization_state;

src/codegen/mips64/macro-assembler-mips64.cc

@@ -6175,40 +6175,6 @@ void TurboAssembler::JumpCodeObject(Register code_object, JumpMode jump_mode) {
 
 namespace {
 
-// Tail-call |function_id| if |actual_state| == |expected_state|
-void TailCallRuntimeIfStateEquals(MacroAssembler* masm, Register actual_state,
-                                  TieringState expected_state,
-                                  Runtime::FunctionId function_id) {
-  ASM_CODE_COMMENT(masm);
-  Label no_match;
-  __ Branch(&no_match, ne, actual_state,
-            Operand(static_cast<int>(expected_state)));
-  __ GenerateTailCallToReturnedCode(function_id);
-  __ bind(&no_match);
-}
-
-void MaybeOptimizeCode(MacroAssembler* masm, Register tiering_state) {
-  // ----------- S t a t e -------------
-  //  -- a0 : actual argument count
-  //  -- a3 : new target (preserved for callee if needed, and caller)
-  //  -- a1 : target function (preserved for callee if needed, and caller)
-  //  -- feedback vector (preserved for caller if needed)
-  //  -- tiering_state : a int32 containing a non-zero optimization
-  //  marker.
-  // -----------------------------------
-  ASM_CODE_COMMENT(masm);
-  DCHECK(!AreAliased(a1, a3, tiering_state));
-
-  TailCallRuntimeIfStateEquals(masm, tiering_state,
-                               TieringState::kRequestTurbofan_Synchronous,
-                               Runtime::kCompileTurbofan_Synchronous);
-  TailCallRuntimeIfStateEquals(masm, tiering_state,
-                               TieringState::kRequestTurbofan_Concurrent,
-                               Runtime::kCompileTurbofan_Concurrent);
-
-  __ stop();
-}
-
 void TailCallOptimizedCodeSlot(MacroAssembler* masm,
                                Register optimized_code_entry, Register scratch1,
                                Register scratch2) {
@@ -6322,7 +6288,7 @@ void MacroAssembler::MaybeOptimizeCodeOrTailCallOptimizedCodeSlot(
     Register optimization_state, Register feedback_vector) {
   ASM_CODE_COMMENT(this);
   Label maybe_has_optimized_code;
-  // Check if optimized code marker is available
+  // Check if optimized code marker is available.
   {
     UseScratchRegisterScope temps(this);
     Register scratch = temps.Acquire();
@@ -6331,14 +6297,13 @@ void MacroAssembler::MaybeOptimizeCodeOrTailCallOptimizedCodeSlot(
     Branch(&maybe_has_optimized_code, eq, scratch, Operand(zero_reg));
   }
 
-  Register tiering_state = optimization_state;
-  DecodeField<FeedbackVector::TieringStateBits>(tiering_state);
-  MaybeOptimizeCode(this, tiering_state);
+  GenerateTailCallToReturnedCode(Runtime::kCompileOptimized);
 
   bind(&maybe_has_optimized_code);
   Register optimized_code_entry = optimization_state;
-  Ld(tiering_state, FieldMemOperand(feedback_vector,
-                                    FeedbackVector::kMaybeOptimizedCodeOffset));
+  Ld(optimized_code_entry,
+     FieldMemOperand(feedback_vector,
+                     FeedbackVector::kMaybeOptimizedCodeOffset));
   TailCallOptimizedCodeSlot(this, optimized_code_entry, t3, a5);
 }